From: deepak.s@linux.intel.com
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 10/10] drm/i915/chv: Freq(opcode) request value for CHV.
Date: Mon, 21 Apr 2014 13:34:14 +0530 [thread overview]
Message-ID: <1398067454-7581-11-git-send-email-deepak.s@linux.intel.com> (raw)
In-Reply-To: <1398067454-7581-2-git-send-email-deepak.s@linux.intel.com>
From: Deepak S <deepak.s@linux.intel.com>
On CHV, All the freq request should be even. S0, we need to make sure we
request the opcode accordingly.
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 9 +++++++++
drivers/gpu/drm/i915/i915_irq.c | 4 ++--
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ead2714..5435d87 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2641,6 +2641,15 @@ timespec_to_jiffies_timeout(const struct timespec *value)
return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}
+/* rps/turbo related */
+static inline int i915_rps_freq_change(struct drm_device *dev)
+{
+ if (IS_CHERRYVIEW(dev))
+ return 2;
+
+ return 1;
+}
+
/*
* If you need to wait X milliseconds between events A and B, but event B
* doesn't happen exactly after event A, you record the timestamp (jiffies) of
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index cf29668..11538fe 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1190,7 +1190,7 @@ static void gen6_pm_rps_work(struct work_struct *work)
if (adj > 0)
adj *= 2;
else
- adj = 1;
+ adj = i915_rps_freq_change(dev_priv->dev);
new_delay = dev_priv->rps.cur_freq + adj;
/*
@@ -1209,7 +1209,7 @@ static void gen6_pm_rps_work(struct work_struct *work)
if (adj < 0)
adj *= 2;
else
- adj = -1;
+ adj = -1 * i915_rps_freq_change(dev_priv->dev);
new_delay = dev_priv->rps.cur_freq + adj;
} else { /* unknown event */
new_delay = dev_priv->rps.cur_freq;
--
1.9.1
next prev parent reply other threads:[~2014-04-21 8:04 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-21 8:04 [PATCH 01/10] drm/i915/bdw: Implement a basic PM interrupt handler deepak.s
2014-04-21 8:04 ` [PATCH 02/10] drm/i915: Enable PM Interrupts target via Display Interface deepak.s
2014-04-25 21:33 ` Ben Widawsky
2014-04-21 8:04 ` [PATCH 03/10] drm/i915/chv: Enable Render Standby (RC6) for Cheeryview deepak.s
2014-04-25 21:42 ` Ben Widawsky
2014-04-25 21:44 ` Ben Widawsky
2014-04-28 15:11 ` Deepak S
2014-04-28 14:29 ` Imre Deak
2014-04-28 14:45 ` Daniel Vetter
2014-04-28 15:02 ` Deepak S
2014-04-28 15:10 ` Deepak S
2014-04-21 8:04 ` [PATCH 04/10] drm/i915/chv: Added CHV specific register read and write deepak.s
2014-04-25 21:54 ` Ben Widawsky
2014-05-05 5:55 ` Deepak S
2014-04-21 8:04 ` [PATCH 05/10] drm/i915/chv: Enable RPS (Turbo) for Cheeryview deepak.s
2014-04-25 22:17 ` Ben Widawsky
2014-04-21 8:04 ` [PATCH 06/10] drm/i915/chv: Streamline CHV forcewake stuff deepak.s
2014-04-25 22:24 ` Ben Widawsky
2014-04-21 8:04 ` [PATCH 07/10] drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0 deepak.s
2014-04-21 8:04 ` [PATCH 08/10] drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV deepak.s
2014-04-25 22:26 ` Ben Widawsky
2014-04-21 8:04 ` [PATCH 09/10] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating deepak.s
2014-04-25 22:28 ` Ben Widawsky
2014-04-21 8:04 ` deepak.s [this message]
2014-04-25 22:32 ` [PATCH 10/10] drm/i915/chv: Freq(opcode) request value for CHV Ben Widawsky
2014-04-25 21:08 ` [PATCH 01/10] drm/i915/bdw: Implement a basic PM interrupt handler Ben Widawsky
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