From: deepak.s@linux.intel.com
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 06/10] drm/i915/chv: Streamline CHV forcewake stuff
Date: Mon, 21 Apr 2014 13:34:10 +0530 [thread overview]
Message-ID: <1398067454-7581-7-git-send-email-deepak.s@linux.intel.com> (raw)
In-Reply-To: <1398067454-7581-2-git-send-email-deepak.s@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Streamline the CHV forcewake functions just like was done for VLV.
This will also fix a bug in accessing the common well registers,
where we'd end up trying to wake up the wells too many times
since we'd call force_wake_get/put twice per register access, with
FORCEFAKE_ALL both times.
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 88 ++++++++++++++-----------------------
1 file changed, 32 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 11741e4..f1264e2 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -619,35 +619,22 @@ chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
unsigned fwengine = 0; \
REG_READ_HEADER(x); \
if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
- fwengine = FORCEWAKE_RENDER; \
- } \
- else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
- fwengine = FORCEWAKE_MEDIA; \
- } \
- else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
- fwengine = FORCEWAKE_ALL; \
- } \
- if (FORCEWAKE_RENDER & fwengine) { \
- if (dev_priv->uncore.fw_rendercount++ == 0) \
- (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
- fwengine); \
- } \
- if (FORCEWAKE_MEDIA & fwengine) { \
- if (dev_priv->uncore.fw_mediacount++ == 0) \
- (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
- fwengine); \
+ if (dev_priv->uncore.fw_rendercount == 0) \
+ fwengine = FORCEWAKE_RENDER; \
+ } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
+ if (dev_priv->uncore.fw_mediacount == 0) \
+ fwengine = FORCEWAKE_MEDIA; \
+ } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
+ if (dev_priv->uncore.fw_rendercount == 0) \
+ fwengine |= FORCEWAKE_RENDER; \
+ if (dev_priv->uncore.fw_mediacount == 0) \
+ fwengine |= FORCEWAKE_MEDIA; \
} \
+ if (fwengine) \
+ dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
val = __raw_i915_read##x(dev_priv, reg); \
- if (FORCEWAKE_RENDER & fwengine) { \
- if (--dev_priv->uncore.fw_rendercount == 0) \
- (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
- fwengine); \
- } \
- if (FORCEWAKE_MEDIA & fwengine) { \
- if (--dev_priv->uncore.fw_mediacount == 0) \
- (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
- fwengine); \
- } \
+ if (fwengine) \
+ dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
REG_READ_FOOTER; \
}
@@ -781,38 +768,27 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
static void \
chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
unsigned fwengine = 0; \
- bool __needs_put = !is_gen8_shadowed(dev_priv, reg); \
+ bool shadowed = is_gen8_shadowed(dev_priv, reg); \
REG_WRITE_HEADER; \
- if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
- fwengine = FORCEWAKE_RENDER; \
- } \
- else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
- fwengine = FORCEWAKE_MEDIA; \
- } \
- else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
- fwengine = FORCEWAKE_ALL; \
- } \
- if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \
- if (dev_priv->uncore.fw_rendercount++ == 0) \
- (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
- fwengine); \
- } \
- if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \
- if (dev_priv->uncore.fw_mediacount++ == 0) \
- (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
- fwengine); \
+ if (!shadowed) { \
+ if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
+ if (dev_priv->uncore.fw_rendercount == 0) \
+ fwengine = FORCEWAKE_RENDER; \
+ } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
+ if (dev_priv->uncore.fw_mediacount == 0) \
+ fwengine = FORCEWAKE_MEDIA; \
+ } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
+ if (dev_priv->uncore.fw_rendercount == 0) \
+ fwengine |= FORCEWAKE_RENDER; \
+ if (dev_priv->uncore.fw_mediacount == 0) \
+ fwengine |= FORCEWAKE_MEDIA; \
+ } \
} \
+ if (fwengine) \
+ dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
__raw_i915_write##x(dev_priv, reg, val); \
- if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \
- if (--dev_priv->uncore.fw_rendercount == 0) \
- (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
- fwengine); \
- } \
- if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \
- if (--dev_priv->uncore.fw_mediacount == 0) \
- (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
- fwengine); \
- } \
+ if (fwengine) \
+ dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
REG_WRITE_FOOTER; \
}
--
1.9.1
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next prev parent reply other threads:[~2014-04-21 8:04 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-21 8:04 [PATCH 01/10] drm/i915/bdw: Implement a basic PM interrupt handler deepak.s
2014-04-21 8:04 ` [PATCH 02/10] drm/i915: Enable PM Interrupts target via Display Interface deepak.s
2014-04-25 21:33 ` Ben Widawsky
2014-04-21 8:04 ` [PATCH 03/10] drm/i915/chv: Enable Render Standby (RC6) for Cheeryview deepak.s
2014-04-25 21:42 ` Ben Widawsky
2014-04-25 21:44 ` Ben Widawsky
2014-04-28 15:11 ` Deepak S
2014-04-28 14:29 ` Imre Deak
2014-04-28 14:45 ` Daniel Vetter
2014-04-28 15:02 ` Deepak S
2014-04-28 15:10 ` Deepak S
2014-04-21 8:04 ` [PATCH 04/10] drm/i915/chv: Added CHV specific register read and write deepak.s
2014-04-25 21:54 ` Ben Widawsky
2014-05-05 5:55 ` Deepak S
2014-04-21 8:04 ` [PATCH 05/10] drm/i915/chv: Enable RPS (Turbo) for Cheeryview deepak.s
2014-04-25 22:17 ` Ben Widawsky
2014-04-21 8:04 ` deepak.s [this message]
2014-04-25 22:24 ` [PATCH 06/10] drm/i915/chv: Streamline CHV forcewake stuff Ben Widawsky
2014-04-21 8:04 ` [PATCH 07/10] drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0 deepak.s
2014-04-21 8:04 ` [PATCH 08/10] drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV deepak.s
2014-04-25 22:26 ` Ben Widawsky
2014-04-21 8:04 ` [PATCH 09/10] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating deepak.s
2014-04-25 22:28 ` Ben Widawsky
2014-04-21 8:04 ` [PATCH 10/10] drm/i915/chv: Freq(opcode) request value for CHV deepak.s
2014-04-25 22:32 ` Ben Widawsky
2014-04-25 21:08 ` [PATCH 01/10] drm/i915/bdw: Implement a basic PM interrupt handler Ben Widawsky
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