From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 03/10] drm/i915/chv: Enable Render Standby (RC6) for Cheeryview Date: Mon, 28 Apr 2014 17:29:46 +0300 Message-ID: <1398695386.17779.12.camel@intelbox> References: <1398067454-7581-2-git-send-email-deepak.s@linux.intel.com> <1398067454-7581-4-git-send-email-deepak.s@linux.intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1967015767==" Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 2B8BB6E68B for ; Mon, 28 Apr 2014 07:29:49 -0700 (PDT) In-Reply-To: <1398067454-7581-4-git-send-email-deepak.s@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: deepak.s@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============1967015767== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-7gtT1ZIzrvrbHV5lnFud" --=-7gtT1ZIzrvrbHV5lnFud Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, 2014-04-21 at 13:34 +0530, deepak.s@linux.intel.com wrote: > From: Deepak S >=20 > v2: Configure PCBR if BIOS fails allocate pcbr (deepak) >=20 > v3: Fix PCBR condition check during CHV RC6 Enable flag set >=20 > Signed-off-by: Deepak S > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 100 ++++++++++++++++++++++++++++++++++= +++++- > 2 files changed, 99 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index b951d61..7090b42 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -5134,6 +5134,7 @@ enum punit_power_well { > #define GEN6_GT_GFX_RC6 0x138108 > #define GEN6_GT_GFX_RC6p 0x13810C > #define GEN6_GT_GFX_RC6pp 0x138110 > +#define VLV_PCBR_ADDR_SHIFT 12 > =20 > #define GEN6_PCODE_MAILBOX 0x138124 > #define GEN6_PCODE_READY (1<<31) > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index f3c5bce..421a4cc 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3264,6 +3264,18 @@ static void gen6_disable_rps(struct drm_device *de= v) > gen6_disable_rps_interrupts(dev); > } > =20 > +static void cherryview_disable_rps(struct drm_device *dev) > +{ > + struct drm_i915_private *dev_priv =3D dev->dev_private; > + > + I915_WRITE(GEN6_RC_CONTROL, 0); > + > + if (dev_priv->vlv_pctx) { > + drm_gem_object_unreference(&dev_priv->vlv_pctx->base); > + dev_priv->vlv_pctx =3D NULL; > + } > +} > + > static void valleyview_disable_rps(struct drm_device *dev) > { > struct drm_i915_private *dev_priv =3D dev->dev_private; > @@ -3642,6 +3654,28 @@ static void valleyview_check_pctx(struct drm_i915_= private *dev_priv) > dev_priv->vlv_pctx->stolen->start); > } > =20 > +static void cherryview_setup_pctx(struct drm_device *dev) > +{ > + struct drm_i915_private *dev_priv =3D dev->dev_private; > + unsigned long pctx_paddr; > + struct i915_gtt *gtt =3D &dev_priv->gtt; > + u32 pcbr; > + int pctx_size =3D 32*1024; > + > + pcbr =3D I915_READ(VLV_PCBR); > + if ((pcbr >> VLV_PCBR_ADDR_SHIFT) =3D=3D 0) { > + /* > + * From the Gunit register HAS: > + * The Gfx driver is expected to program this register and ensure > + * proper allocation within Gfx stolen memory. For example, this > + * register should be programmed such than the PCBR range does not > + * overlap with other relevant ranges. > + */ > + pctx_paddr =3D (dev_priv->mm.stolen_base + gtt->stolen_size - pctx_siz= e); This area should be reserved. > + I915_WRITE(VLV_PCBR, pctx_paddr); > + } > +} > + > static void valleyview_setup_pctx(struct drm_device *dev) > { > struct drm_i915_private *dev_priv =3D dev->dev_private; > @@ -3697,6 +3731,61 @@ static void valleyview_cleanup_pctx(struct drm_dev= ice *dev) > dev_priv->vlv_pctx =3D NULL; > } > =20 > +static void cherryview_enable_rps(struct drm_device *dev) > +{ > + struct drm_i915_private *dev_priv =3D dev->dev_private; > + struct intel_ring_buffer *ring; > + u32 gtfifodbg, rc6_mode =3D 0, pcbr; > + int i; > + > + WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); > + > + if ((gtfifodbg =3D I915_READ(GTFIFODBG))) { > + DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", > + gtfifodbg); > + I915_WRITE(GTFIFODBG, gtfifodbg); > + } > + > + cherryview_setup_pctx(dev); This should be called from intel_init_gt_powersave(). > + > + /* 1a & 1b: Get forcewake during program sequence. Although the driver > + * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ > + gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); > + > + /* 2a: Program RC6 thresholds.*/ > + I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); > + I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ > + I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ > + > + for_each_ring(ring, dev_priv, i) > + I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); > + > + I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ > + > + /* allows RC6 residency counter to work */ > + I915_WRITE(VLV_COUNTER_CONTROL, > + _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | > + VLV_MEDIA_RC6_COUNT_EN | > + VLV_RENDER_RC6_COUNT_EN)); > + > + /* Todo: If BIOS has not configured PCBR > + * then allocate in BIOS Reserved */ > + > + /* For now we assume BIOS is allocating and populating the PCBR */ > + pcbr =3D I915_READ(VLV_PCBR); > + > + DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr); > + > + /* 3: Enable RC6 */ > + if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) && > + (pcbr >> VLV_PCBR_ADDR_SHIFT)) This may break runtime PM, if PCBR isn't setup, since we assume that if intel_enable_rc6() returns a non-zero value RC6 will be truly enabled. So the check for PCBR should be moved to sanitize_rc6_option(). Also note that for CHV PCBR setup cannot fail atm. > + rc6_mode =3D GEN6_RC_CTL_EI_MODE(1) | VLV_RC_CTL_CTX_RST_PARALLEL; > + > + I915_WRITE(GEN6_RC_CONTROL, rc6_mode); > + > + gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); > +} > + > static void valleyview_enable_rps(struct drm_device *dev) > { > struct drm_i915_private *dev_priv =3D dev->dev_private; > @@ -4550,7 +4639,9 @@ void intel_disable_gt_powersave(struct drm_device *= dev) > cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work); > cancel_work_sync(&dev_priv->rps.work); > mutex_lock(&dev_priv->rps.hw_lock); > - if (IS_VALLEYVIEW(dev)) > + if (IS_CHERRYVIEW(dev)) > + cherryview_disable_rps(dev); > + else if (IS_VALLEYVIEW(dev)) > valleyview_disable_rps(dev); > else > gen6_disable_rps(dev); > @@ -4568,7 +4659,9 @@ static void intel_gen6_powersave_work(struct work_s= truct *work) > =20 > mutex_lock(&dev_priv->rps.hw_lock); > =20 > - if (IS_VALLEYVIEW(dev)) { > + if (IS_CHERRYVIEW(dev)) { > + cherryview_enable_rps(dev); > + } else if (IS_VALLEYVIEW(dev)) { > valleyview_enable_rps(dev); > } else if (IS_BROADWELL(dev)) { > gen8_enable_rps(dev); > @@ -4590,6 +4683,8 @@ void intel_enable_gt_powersave(struct drm_device *d= ev) > ironlake_enable_rc6(dev); > intel_init_emon(dev); > } else if (IS_GEN6(dev) || IS_GEN7(dev)) { > + if (IS_VALLEYVIEW(dev)) > + valleyview_setup_pctx(dev); Spurious hunk, as Ben pointed out, and the GEN check will be false for CherryView. The corresponding GEN check must be updated in intel_disable_gt_powersave() too. > /* > * PCU communication is slow and this doesn't need to be > * done at any specific time, so do this out of our fast path > @@ -5175,6 +5270,7 @@ static void valleyview_init_clock_gating(struct drm= _device *dev) > dev_priv->mem_freq =3D 1333; > break; > } > + > DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq); > =20 > dev_priv->vlv_cdclk_freq =3D valleyview_cur_cdclk(dev_priv); --=-7gtT1ZIzrvrbHV5lnFud Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJTXmXaAAoJEORIIAnNuWDFe9UIAIXKfAwOJ6OhK86zFrpxg9S8 pQDKF62erQjoVkIPUjFSWlNJ7kIVgycwG2mhrhReiQnrcXCYMNK3z/c2lmwMxKKg I0a2Wcl35HcQ0A9tGbU9NAMeWuKx35mVjvAhzcL5aXl8LkM+6ZI43R0auGyI7SSE bhQ2/4e6yfHpl13DgIOSDl2lrTeiK+7qQvaZz6VjSXYZc9z/D73FJ73hCJOgkT5l jPwGpKG8HgWWj+K1nK5QIpRd9y0DCGfXtWE4gSqt+JMr/7WnG8ydOLN/w9XFnPlp jDIYv93kMTQLVkNCvWKgKmoiDay5ysevqqHhw7470VxvGK/ef577CR98tnpAhYw= =iTxc -----END PGP SIGNATURE----- --=-7gtT1ZIzrvrbHV5lnFud-- --===============1967015767== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============1967015767==--