From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 19/71] drm/i915/chv: Trigger phy common lane reset Date: Mon, 28 Apr 2014 17:54:24 +0300 Message-ID: <1398696864.17779.21.camel@intelbox> References: <1397039349-10639-1-git-send-email-ville.syrjala@linux.intel.com> <1397039349-10639-20-git-send-email-ville.syrjala@linux.intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1758454160==" Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 59DE36E0F1 for ; Mon, 28 Apr 2014 07:56:11 -0700 (PDT) In-Reply-To: <1397039349-10639-20-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============1758454160== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-Ail8OBC1YvUFFFLBXs0Y" --=-Ail8OBC1YvUFFFLBXs0Y Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 2014-04-09 at 13:28 +0300, ville.syrjala@linux.intel.com wrote: > From: Chon Ming Lee >=20 > During cold boot, the display controller needs to deassert the common > lane reset. Only do it once during intel_init_dpio for both PHYx2 and > PHYx1. >=20 > Besides, assert the common lane reset when disable pll. This still > to be determined whether need to do it by driver. >=20 > Signed-off-by: Chon Ming Lee > [vsyrjala: Don't disable DPIO PLL when using DSI] > [vsyrjala: Don't call vlv_disable_pll() by accident on CHV] > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 > --- > drivers/gpu/drm/i915/i915_reg.h | 8 +++++ > drivers/gpu/drm/i915/intel_display.c | 66 ++++++++++++++++++++++++++++--= ------ > 2 files changed, 59 insertions(+), 15 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index 8aea092..8fcf4ea 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1391,6 +1391,14 @@ enum punit_power_well { > /* Additional CHV pll/phy registers */ > #define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240) > #define DPLL_PORTD_READY_MASK (0xf) > +#define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100) > +#define PHY_COM_LANE_RESET_DEASSERT(phy, val) \ > + ((phy =3D=3D DPIO_PHY0) ? (val | 1) : (val | 2)) > +#define PHY_COM_LANE_RESET_ASSERT(phy, val) \ > + ((phy =3D=3D DPIO_PHY0) ? (val & ~1) : (val & ~2)) > +#define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104) > +#define PHY_POWERGOOD(phy) ((phy =3D=3D DPIO_PHY0) ? (1<<31) : (1<<30)= ) > + > /* > * The i830 generation, in LVDS mode, defines P1 as the bit number set w= ithin > * this field (only one bit may be set). > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index 153f244..e33667d 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1395,17 +1395,36 @@ static void intel_reset_dpio(struct drm_device *d= ev) > DPLL_REFA_CLK_ENABLE_VLV | > DPLL_INTEGRATED_CRI_CLK_VLV); > =20 > - /* > - * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - > - * 6. De-assert cmn_reset/side_reset. Same as VLV X0. > - * a. GUnit 0x2110 bit[0] set to 1 (def 0) > - * b. The other bits such as sfr settings / modesel may all be set > - * to 0. This is VLV specific, so ok to be moved, > - * > - * This should only be done on init and resume from S3 with both > - * PLLs disabled, or we risk losing DPIO and PLL synchronization. > - */ but this is also true for CHV, so should stay. > - I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); > + if (IS_CHERRYVIEW(dev)) { > + enum dpio_phy phy; > + u32 val; > + > + for (phy =3D DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) { > + /* Poll for phypwrgood signal */ > + if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & > + PHY_POWERGOOD(phy), 1)) > + DRM_ERROR("Display PHY %d is not power up\n", phy); > + > + /* Deassert common lane reset for PHY*/ > + val =3D I915_READ(DISPLAY_PHY_CONTROL); > + I915_WRITE(DISPLAY_PHY_CONTROL, > + PHY_COM_LANE_RESET_DEASSERT(phy, val)); Would be clearer not to hide the 'or' in the macro and let PHY_COM_LANE_RESET_DEASSERT be just the flag itself and do here I915_WRITE(DISPLAY_PHY_CONTROL, val | PHY_COM_LANE_RESET_DEASSERT(phy)); The above issues are minor, so even without fixing them this patch is Reviewed-by: Imre Deak > + } > + > + } else { > + /* > + * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - > + * 6. De-assert cmn_reset/side_reset. Same as VLV X0. > + * a. GUnit 0x2110 bit[0] set to 1 (def 0) > + * b. The other bits such as sfr settings / modesel may all > + * be set to 0. > + * > + * This should only be done on init and resume from S3 with > + * both PLLs disabled, or we risk losing DPIO and PLL > + * synchronization. > + */ > + I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); > + } > } > =20 > static void vlv_enable_pll(struct intel_crtc *crtc) > @@ -1529,6 +1548,19 @@ static void vlv_disable_pll(struct drm_i915_privat= e *dev_priv, enum pipe pipe) > val =3D DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; > I915_WRITE(DPLL(pipe), val); > POSTING_READ(DPLL(pipe)); > + > +} > + > +static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe= pipe) > +{ > + int dpll =3D DPLL(pipe); > + u32 val; > + > + /* Set PLL en =3D 0 */ > + val =3D I915_READ(dpll); > + val &=3D ~DPLL_VCO_ENABLE; > + I915_WRITE(dpll, val); > + > } > =20 > void vlv_wait_port_ready(struct drm_i915_private *dev_priv, > @@ -4511,10 +4543,14 @@ static void i9xx_crtc_disable(struct drm_crtc *cr= tc) > if (encoder->post_disable) > encoder->post_disable(encoder); > =20 > - if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) > - vlv_disable_pll(dev_priv, pipe); > - else if (!IS_VALLEYVIEW(dev)) > - i9xx_disable_pll(dev_priv, pipe); > + if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) { > + if (IS_CHERRYVIEW(dev)) > + chv_disable_pll(dev_priv, pipe); > + else if (IS_VALLEYVIEW(dev)) > + vlv_disable_pll(dev_priv, pipe); > + else > + i9xx_disable_pll(dev_priv, pipe); > + } > =20 > intel_crtc->active =3D false; > intel_update_watermarks(crtc); --=-Ail8OBC1YvUFFFLBXs0Y Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJTXmugAAoJEORIIAnNuWDFn7UIAIswaDelKP6IiWnsjvTXrlq8 Xl3PR1/9NwYfUnj9RkpXvhy9XaOENa9XAh/K8kcaIk2Nzzm4o7LgmyVpT4gRLJcd KfRlPRv2UPkIHeCNzImV0wQ387h0Y0+CMsgzLqzm5rrrqYuv0NX1PsTmtMSbP00y KhSUjgOM5fjBim2U//rZUbat74NZb1Z4y68hu7rbkyHjuy8N6JzgE21kWewQMiQC Qw3Pjq7U4/apjf1aSs5aTxaFcaatBBtfQsFbLUsDWFg8a5F1Rwf3kA3Rjx0/KYhY 8Gb/sAGJLikQPK/jyJaJLwRfU3HpLcgn5fzHCRhiAi+VEIno12eO/GMExPMoSzc= =WFK1 -----END PGP SIGNATURE----- --=-Ail8OBC1YvUFFFLBXs0Y-- --===============1758454160== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============1758454160==--