From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 20/71] drm/i915/chv: find the best divisor for the target clock v4 Date: Tue, 29 Apr 2014 17:56:52 +0300 Message-ID: <1398783412.27083.21.camel@intelbox> References: <1397039349-10639-1-git-send-email-ville.syrjala@linux.intel.com> <1397039349-10639-21-git-send-email-ville.syrjala@linux.intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============2046788740==" Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 0EA496E0FA for ; Tue, 29 Apr 2014 07:56:56 -0700 (PDT) In-Reply-To: <1397039349-10639-21-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============2046788740== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-b5FLiZCr97FNHMUeh36y" --=-b5FLiZCr97FNHMUeh36y Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 2014-04-09 at 13:28 +0300, ville.syrjala@linux.intel.com wrote: > From: Chon Ming Lee >=20 > Based on the chv clock limit, find the best divisor. >=20 > The divisor data has been verified with this spreadsheet. > P1273_DPLL_Programming Spreadsheet. >=20 > v2: Rebase the code and change the chv_find_best_dpll based on new > standard way to use intel_PLL_is_valid. Besides, clean up some extra > variables. >=20 > v3: Ville suggest better fixed point for m2 calculation. >=20 > v4: -Add comment for the limit is compute using fast clock. (Ville) > -Don't pass the request clock to chv_clock, as the same function will > be use clock readout, which doens't have request clock. (Ville) > -Add and use DIV_ROUND_CLOSEST_ULL to consistent with other clock > calculation. (Ville) > -Fix the dp m2 after m2 has stored fixed point. (Ville) >=20 > Signed-off-by: Chon Ming Lee > [vsyrjala: Avoid div-by-zero in chv_clock()] > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 Took a while to understand all the different clock rates along the path, but it looks ok: Reviewed-by: Imre Deak > --- > drivers/gpu/drm/i915/intel_display.c | 86 ++++++++++++++++++++++++++++++= ++++++ > drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++ > 2 files changed, 107 insertions(+) >=20 > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index e33667d..d73fec5 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -41,6 +41,9 @@ > #include > #include > =20 > +#define DIV_ROUND_CLOSEST_ULL(ll, d) \ > + ({ unsigned long long _tmp =3D (ll)+(d)/2; do_div(_tmp, d); _tmp; }) > + > static void intel_increase_pllclock(struct drm_crtc *crtc); > static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); > =20 > @@ -328,6 +331,22 @@ static const intel_limit_t intel_limits_vlv =3D { > .p2 =3D { .p2_slow =3D 2, .p2_fast =3D 20 }, /* slow=3Dmin, fast=3Dmax = */ > }; > =20 > +static const intel_limit_t intel_limits_chv =3D { > + /* > + * These are the data rate limits (measured in fast clocks) > + * since those are the strictest limits we have. The fast > + * clock and actual rate limits are more relaxed, so checking > + * them would make no difference. > + */ > + .dot =3D { .min =3D 25000 * 5, .max =3D 540000 * 5}, > + .vco =3D { .min =3D 4860000, .max =3D 6700000 }, > + .n =3D { .min =3D 1, .max =3D 1 }, > + .m1 =3D { .min =3D 2, .max =3D 2 }, > + .m2 =3D { .min =3D 24 << 22, .max =3D 175 << 22 }, > + .p1 =3D { .min =3D 2, .max =3D 4 }, > + .p2 =3D { .p2_slow =3D 1, .p2_fast =3D 14 }, > +}; > + > static void vlv_clock(int refclk, intel_clock_t *clock) > { > clock->m =3D clock->m1 * clock->m2; > @@ -412,6 +431,8 @@ static const intel_limit_t *intel_limit(struct drm_cr= tc *crtc, int refclk) > limit =3D &intel_limits_pineview_lvds; > else > limit =3D &intel_limits_pineview_sdvo; > + } else if (IS_CHERRYVIEW(dev)) { > + limit =3D &intel_limits_chv; > } else if (IS_VALLEYVIEW(dev)) { > limit =3D &intel_limits_vlv; > } else if (!IS_GEN2(dev)) { > @@ -456,6 +477,17 @@ static void i9xx_clock(int refclk, intel_clock_t *cl= ock) > clock->dot =3D DIV_ROUND_CLOSEST(clock->vco, clock->p); > } > =20 > +static void chv_clock(int refclk, intel_clock_t *clock) > +{ > + clock->m =3D clock->m1 * clock->m2; > + clock->p =3D clock->p1 * clock->p2; > + if (WARN_ON(clock->n =3D=3D 0 || clock->p =3D=3D 0)) > + return; > + clock->vco =3D DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, > + clock->n << 22); > + clock->dot =3D DIV_ROUND_CLOSEST(clock->vco, clock->p); > +} > + > #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } wh= ile (0) > /** > * Returns whether the given set of divisors are valid for a given refcl= k with > @@ -731,6 +763,58 @@ vlv_find_best_dpll(const intel_limit_t *limit, struc= t drm_crtc *crtc, > return found; > } > =20 > +static bool > +chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, > + int target, int refclk, intel_clock_t *match_clock, > + intel_clock_t *best_clock) > +{ > + struct drm_device *dev =3D crtc->dev; > + intel_clock_t clock; > + uint64_t m2; > + int found =3D false; > + > + memset(best_clock, 0, sizeof(*best_clock)); > + > + /* > + * Based on hardware doc, the n always set to 1, and m1 always > + * set to 2. If requires to support 200Mhz refclk, we need to > + * revisit this because n may not 1 anymore. > + */ > + clock.n =3D 1, clock.m1 =3D 2; > + target *=3D 5; /* fast clock */ > + > + for (clock.p1 =3D limit->p1.max; clock.p1 >=3D limit->p1.min; clock.p1-= -) { > + for (clock.p2 =3D limit->p2.p2_fast; > + clock.p2 >=3D limit->p2.p2_slow; > + clock.p2 -=3D clock.p2 > 10 ? 2 : 1) { > + > + clock.p =3D clock.p1 * clock.p2; > + > + m2 =3D DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * > + clock.n) << 22, refclk * clock.m1); > + > + if (m2 > INT_MAX/clock.m1) > + continue; > + > + clock.m2 =3D m2; > + > + chv_clock(refclk, &clock); > + > + if (!intel_PLL_is_valid(dev, limit, &clock)) > + continue; > + > + /* based on hardware requirement, prefer bigger p > + */ > + if (clock.p > best_clock->p) { > + *best_clock =3D clock; > + found =3D true; > + } > + } > + } > + > + return found; > +} > + > bool intel_crtc_active(struct drm_crtc *crtc) > { > struct intel_crtc *intel_crtc =3D to_intel_crtc(crtc); > @@ -11031,6 +11115,8 @@ static void intel_init_display(struct drm_device = *dev) > =20 > if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) > dev_priv->display.find_dpll =3D g4x_find_best_dpll; > + else if (IS_CHERRYVIEW(dev)) > + dev_priv->display.find_dpll =3D chv_find_best_dpll; > else if (IS_VALLEYVIEW(dev)) > dev_priv->display.find_dpll =3D vlv_find_best_dpll; > else if (IS_PINEVIEW(dev)) > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel= _dp.c > index c33971e..6be7b35 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -64,6 +64,24 @@ static const struct dp_link_dpll vlv_dpll[] =3D { > { .p1 =3D 2, .p2 =3D 2, .n =3D 1, .m1 =3D 2, .m2 =3D 27 } } > }; > =20 > +/* > + * CHV supports eDP 1.4 that have more link rates. > + * Below only provides the fixed rate but exclude variable rate. > + */ > +static const struct dp_link_dpll chv_dpll[] =3D { > + /* > + * CHV requires to program fractional division for m2. > + * m2 is stored in fixed point format using formula below > + * (m2_int << 22) | m2_fraction > + */ > + { DP_LINK_BW_1_62, /* m2_int =3D 32, m2_fraction =3D 1677722 */ > + { .p1 =3D 4, .p2 =3D 2, .n =3D 1, .m1 =3D 2, .m2 =3D 0x819999a } }, > + { DP_LINK_BW_2_7, /* m2_int =3D 27, m2_fraction =3D 0 */ > + { .p1 =3D 4, .p2 =3D 1, .n =3D 1, .m1 =3D 2, .m2 =3D 0x6c00000 } }, > + { DP_LINK_BW_5_4, /* m2_int =3D 27, m2_fraction =3D 0 */ > + { .p1 =3D 2, .p2 =3D 1, .n =3D 1, .m1 =3D 2, .m2 =3D 0x6c00000 } } > +}; > + > /** > * is_edp - is the given port attached to an eDP panel (either CPU or PC= H) > * @intel_dp: DP struct > @@ -720,6 +738,9 @@ intel_dp_set_clock(struct intel_encoder *encoder, > } else if (HAS_PCH_SPLIT(dev)) { > divisor =3D pch_dpll; > count =3D ARRAY_SIZE(pch_dpll); > + } else if (IS_CHERRYVIEW(dev)) { > + divisor =3D chv_dpll; > + count =3D ARRAY_SIZE(chv_dpll); > } else if (IS_VALLEYVIEW(dev)) { > divisor =3D vlv_dpll; > count =3D ARRAY_SIZE(vlv_dpll); --=-b5FLiZCr97FNHMUeh36y Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJTX720AAoJEORIIAnNuWDF0nsIAMTuqIwyq7HNGtCU6trcFzm1 Hjk7HVeAK+tiKCOBCm6jVmvgAq/3TQfSYEwPH8d6BYdsVPf4qSSGtpZG+g16tkIb woQs0DdYPYBLV1iaXXwjvz02QE5/3kpSHzNcn0CQzTwWcx0EAun3uacPbIC7ttmF vQ+XnTmYl+qgh8KETG2iY1iq33Ra6akadqeooZyQU9t83s0prY8QK4eCPKC14t+b 9gpkMqR4liz+RanFprDSgng4efESvuajTguJYippN1aYhCN2+8U7yIIvKVyp0lr5 pEqYxmoSLgTcyGSpsVNeeMWpGubV1AF5rJslfRPvFeyEk9Et0zneMS804QXF1kY= =aBrW -----END PGP SIGNATURE----- --=-b5FLiZCr97FNHMUeh36y-- --===============2046788740== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============2046788740==--