From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 23/71] drm/i915/chv: Pipe select change for DP and HDMI Date: Wed, 30 Apr 2014 15:49:57 +0300 Message-ID: <1398862197.6163.8.camel@intelbox> References: <1397039349-10639-1-git-send-email-ville.syrjala@linux.intel.com> <1397039349-10639-24-git-send-email-ville.syrjala@linux.intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0708173906==" Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 0309A7201B for ; Wed, 30 Apr 2014 05:49:59 -0700 (PDT) In-Reply-To: <1397039349-10639-24-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0708173906== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-4w+hFl0Oo8AmrywP8F10" --=-4w+hFl0Oo8AmrywP8F10 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 2014-04-09 at 13:28 +0300, ville.syrjala@linux.intel.com wrote: > From: Chon Ming Lee >=20 > With additional of pipe C, current 1 bit registers for pipe select > for HDMI and DP are no longer able to gather for 3 pipes. As a result, > new bits location in the same registers are added. >=20 > For HDMI, VLV uses bit 30, CHV uses bit 24-25. >=20 > For DP, VLV uses bit 30, CHV uses bit 16-17. >=20 > Reviewed-by: Ville Syrj=C3=A4l=C3=A4 > Signed-off-by: Chon Ming Lee Reviewed-by: Imre Deak > --- > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ > drivers/gpu/drm/i915/intel_display.c | 6 ++++++ > drivers/gpu/drm/i915/intel_dp.c | 8 ++++++-- > drivers/gpu/drm/i915/intel_hdmi.c | 2 ++ > 4 files changed, 20 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index 75f31f5..91c8fac 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2478,6 +2478,10 @@ enum punit_power_well { > #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) > #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) > =20 > +/* CHV SDVO/HDMI bits: */ > +#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) > +#define SDVO_PIPE_SEL_MASK_CHV (3 << 24) > + > =20 > /* DVO port control */ > #define DVOA 0x61120 > @@ -3235,6 +3239,8 @@ enum punit_power_well { > #define DP_PORT_EN (1 << 31) > #define DP_PIPEB_SELECT (1 << 30) > #define DP_PIPE_MASK (1 << 30) > +#define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16) > +#define DP_PIPE_MASK_CHV (3 << 16) > =20 > /* Link training mode - select a suitable mode for each stage */ > #define DP_LINK_TRAIN_PAT_1 (0 << 28) > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index 36d6e212..f849c65 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1337,6 +1337,9 @@ static bool dp_pipe_enabled(struct drm_i915_private= *dev_priv, > u32 trans_dp_ctl =3D I915_READ(trans_dp_ctl_reg); > if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) !=3D port_sel) > return false; > + } else if (IS_CHERRYVIEW(dev_priv->dev)) { > + if ((val & DP_PIPE_MASK_CHV) !=3D DP_PIPE_SELECT_CHV(pipe)) > + return false; > } else { > if ((val & DP_PIPE_MASK) !=3D (pipe << 30)) > return false; > @@ -1353,6 +1356,9 @@ static bool hdmi_pipe_enabled(struct drm_i915_priva= te *dev_priv, > if (HAS_PCH_CPT(dev_priv->dev)) { > if ((val & SDVO_PIPE_SEL_MASK_CPT) !=3D SDVO_PIPE_SEL_CPT(pipe)) > return false; > + } else if (IS_CHERRYVIEW(dev_priv->dev)) { > + if ((val & SDVO_PIPE_SEL_MASK_CHV) !=3D SDVO_PIPE_SEL_CHV(pipe)) > + return false; > } else { > if ((val & SDVO_PIPE_SEL_MASK) !=3D SDVO_PIPE_SEL(pipe)) > return false; > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel= _dp.c > index 71a4fa2..21ac845 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -964,8 +964,12 @@ static void intel_dp_mode_set(struct intel_encoder *= encoder) > if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) > intel_dp->DP |=3D DP_ENHANCED_FRAMING; > =20 > - if (crtc->pipe =3D=3D 1) > - intel_dp->DP |=3D DP_PIPEB_SELECT; > + if (!IS_CHERRYVIEW(dev)) { > + if (crtc->pipe =3D=3D 1) > + intel_dp->DP |=3D DP_PIPEB_SELECT; > + } else { > + intel_dp->DP |=3D DP_PIPE_SELECT_CHV(crtc->pipe); > + } > } else { > intel_dp->DP |=3D DP_LINK_TRAIN_OFF_CPT; > } > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/int= el_hdmi.c > index bbda011..9f868f4 100644 > --- a/drivers/gpu/drm/i915/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > @@ -652,6 +652,8 @@ static void intel_hdmi_mode_set(struct intel_encoder = *encoder) > =20 > if (HAS_PCH_CPT(dev)) > hdmi_val |=3D SDVO_PIPE_SEL_CPT(crtc->pipe); > + else if (IS_CHERRYVIEW(dev)) > + hdmi_val |=3D SDVO_PIPE_SEL_CHV(crtc->pipe); > else > hdmi_val |=3D SDVO_PIPE_SEL(crtc->pipe); > =20 --=-4w+hFl0Oo8AmrywP8F10 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJTYPF1AAoJEORIIAnNuWDFYxIH/0tAn/eRpaa4gjLBHm8DauUe jEzgTTc0JhO021gv/TzAgeN9gRrfOsIKB4GiH09FTS0odEkswjvqQMXp90fNFhGk CQXpW3TeQiTSg812CTHRlhCXZH1akvE8uwNMnyMKYRSmqWhecHORMpyqNpH21eRV 1sKx2e8vGMentzFgWvCjr1CGpc/V1633EbeokWE/g1mOGuNExAqGWxxIRaq4IcBn HLPC0HENYxy8oJg6KE294n1Oi6LxRZRZn3UsX0+Kies/851MTPHC+clMbn1xo3UW XaII0hRYksb/CAr6jBf5XsUBrgYXgFcuzGDS+Fn6Y1Bpku1Q2dBGtZ3xBMiLw+s= =2BxK -----END PGP SIGNATURE----- --=-4w+hFl0Oo8AmrywP8F10-- --===============0708173906== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0708173906==--