From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 24/71] drm/i915/chv: Add DPLL state readout support Date: Wed, 30 Apr 2014 16:11:27 +0300 Message-ID: <1398863487.6163.15.camel@intelbox> References: <1397039349-10639-1-git-send-email-ville.syrjala@linux.intel.com> <1397039349-10639-25-git-send-email-ville.syrjala@linux.intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1579389056==" Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id A15A16E188 for ; Wed, 30 Apr 2014 06:11:30 -0700 (PDT) In-Reply-To: <1397039349-10639-25-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============1579389056== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-kvk5IrhHn50hF0U11Ubr" --=-kvk5IrhHn50hF0U11Ubr Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 2014-04-09 at 13:28 +0300, ville.syrjala@linux.intel.com wrote: > From: Ville Syrj=C3=A4l=C3=A4 >=20 > Add chv_crtc_clock_get() to read out the DPLL settings. >=20 > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 > --- > drivers/gpu/drm/i915/intel_display.c | 34 ++++++++++++++++++++++++++++++= +++- > 1 file changed, 33 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index f849c65..266d8fe 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -6062,6 +6062,36 @@ static void i9xx_get_plane_config(struct intel_crt= c *crtc, > =20 > } > =20 > +static void chv_crtc_clock_get(struct intel_crtc *crtc, > + struct intel_crtc_config *pipe_config) > +{ > + struct drm_device *dev =3D crtc->base.dev; > + struct drm_i915_private *dev_priv =3D dev->dev_private; > + int pipe =3D pipe_config->cpu_transcoder; > + enum dpio_channel port =3D vlv_pipe_to_channel(pipe); 'ch' would be clearer. > + intel_clock_t clock; > + u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; > + int refclk =3D 100000; > + > + mutex_lock(&dev_priv->dpio_lock); > + cmn_dw13 =3D vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); > + pll_dw0 =3D vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); > + pll_dw1 =3D vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); > + pll_dw2 =3D vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); > + mutex_unlock(&dev_priv->dpio_lock); > + > + clock.m1 =3D (pll_dw1 & 0x7) =3D=3D DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; > + clock.m2 =3D ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); > + clock.n =3D (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; > + clock.p1 =3D (cmn_dw13 >> DPIO_CHV_P1_SHIFT) & 0x7; > + clock.p2 =3D (cmn_dw13 >> DPIO_CHV_P2_SHIFT) & 0x1f; We could throw in a check here for the rest of the dividers that we assume fixed (S1, K, div_by2, div_by4). With or without the above changes: Reviewed-by: Imre Deak > + > + chv_clock(refclk, &clock); > + > + /* clock.dot is the fast clock */ > + pipe_config->port_clock =3D clock.dot / 5; > +} > + > static bool i9xx_get_pipe_config(struct intel_crtc *crtc, > struct intel_crtc_config *pipe_config) > { > @@ -6131,7 +6161,9 @@ static bool i9xx_get_pipe_config(struct intel_crtc = *crtc, > DPLL_PORTB_READY_MASK); > } > =20 > - if (IS_VALLEYVIEW(dev)) > + if (IS_CHERRYVIEW(dev)) > + chv_crtc_clock_get(crtc, pipe_config); > + else if (IS_VALLEYVIEW(dev)) > vlv_crtc_clock_get(crtc, pipe_config); > else > i9xx_crtc_clock_get(crtc, pipe_config); --=-kvk5IrhHn50hF0U11Ubr Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJTYPZ/AAoJEORIIAnNuWDFbZ0IAMA36zGh3n39T7mMj2ci953h XoebDfuTv2GFzi/pCT0mZAs0UQRHekBGJrlEAklmSYcwiC0XkAPZ+YseFmiPiFDV NVKV9Bve+nOm787DGEHz4kwxpMsNcjiKFk/EodXC4v3D1FIxP99AJ+1xhlRPFvLt TGMFMIdK75QFr+/6uw5XiZllSLQKYvPXQq66gwejKuuoBpSIWCAb193RGnNkd+PQ DoPk9nPt0cUw3OKuZ+aECBxVK8TjMiFRvG6GGsvgQblGkplc6QC1RjOO2vY+ZPOS PhbBaxjkw/ko+Tlc2R7EKUrnG9U/WQqlK2M1Gj1KEmMMKy+46jouL8FYRlO1Tak= =HyyU -----END PGP SIGNATURE----- --=-kvk5IrhHn50hF0U11Ubr-- --===============1579389056== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============1579389056==--