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From: deepak.s@linux.intel.com
To: intel-gfx@lists.freedesktop.org
Cc: fafael.barbalho@intel.com
Subject: [PATCH 09/10] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating
Date: Mon,  5 May 2014 18:17:38 +0530	[thread overview]
Message-ID: <1399294059-20748-10-git-send-email-deepak.s@linux.intel.com> (raw)
In-Reply-To: <1399294059-20748-1-git-send-email-deepak.s@linux.intel.com>

From: Deepak S <deepak.s@linux.intel.com>

Signed-off-by: Deepak S <deepak.s@linux.intel.com>
[vsyrjala: Fix merge fubmle where the code ended up in
g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index dedbdf3..0d9b831 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3985,7 +3985,18 @@ static void cherryview_enable_rps(struct drm_device *dev)
 		   GEN6_RP_UP_BUSY_AVG |
 		   GEN6_RP_DOWN_IDLE_AVG);
 
+	/* ToDo: Update the mem freq based on latest spec [CHV]*/
 	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+	switch ((val >> 6) & 3) {
+	case 0:
+	case 1:
+	case 2:
+		dev_priv->mem_freq = 1600;
+		break;
+	case 3:
+		dev_priv->mem_freq = 2000;
+		break;
+	}
 
 	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
 	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
-- 
1.9.1

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  parent reply	other threads:[~2014-05-05 12:48 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-05-05 12:47 [PATCH 00/10] Enable RC6/Turbo on CHV deepak.s
2014-05-05 12:47 ` [PATCH 01/10] drm/i915/bdw: Implement a basic PM interrupt handler deepak.s
2014-05-07 13:58   ` Ville Syrjälä
2014-05-05 12:47 ` [PATCH 02/10] drm/i915: Enable PM Interrupts target via Display Interface deepak.s
2014-05-07 14:08   ` Ville Syrjälä
2014-05-14 15:37   ` [PATCH v3] " deepak.s
2014-05-14 15:47     ` Ville Syrjälä
2014-05-05 12:47 ` [PATCH 03/10] drm/i915/chv: Enable Render Standby (RC6) for Cherryview deepak.s
2014-05-09 13:19   ` Mika Kuoppala
2014-05-14 15:47     ` Deepak S
2014-05-15  9:57   ` [PATCH v5] " deepak.s
2014-05-15 10:00     ` Deepak S
2014-05-15 10:16     ` Mika Kuoppala
2014-05-15 10:22       ` Mika Kuoppala
2014-05-15 12:38       ` [PATCH v5 1/8] " deepak.s
2014-05-05 12:47 ` [PATCH 04/10] drm/i915/chv: Added CHV specific register read and write deepak.s
2014-05-16 14:46   ` Mika Kuoppala
2014-05-05 12:47 ` [PATCH 05/10] drm/i915/chv: Streamline CHV forcewake stuff deepak.s
2014-05-05 12:47 ` [PATCH 06/10] drm/i915/chv: Enable RPS (Turbo) for Cherryview deepak.s
2014-05-05 12:47 ` [PATCH 07/10] drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0 deepak.s
2014-05-05 12:47 ` [PATCH 08/10] drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV deepak.s
2014-05-05 12:47 ` deepak.s [this message]
2014-05-05 12:47 ` [PATCH 10/10] drm/i915/chv: Freq(opcode) request for CHV deepak.s
2014-05-07 14:23   ` Ville Syrjälä
2014-05-12 13:53   ` [PATCH v2] " deepak.s
2014-05-15 21:22 ` [PATCH 00/10] Enable RC6/Turbo on CHV Daniel Vetter
  -- strict thread matches above, loose matches on Subject: below --
2014-04-21  8:04 [PATCH 01/10] drm/i915/bdw: Implement a basic PM interrupt handler deepak.s
2014-04-21  8:04 ` [PATCH 09/10] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating deepak.s
2014-04-25 22:28   ` Ben Widawsky

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