From: deepak.s@linux.intel.com
To: intel-gfx@lists.freedesktop.org
Cc: fafael.barbalho@intel.com
Subject: [PATCH 05/10] drm/i915/chv: Streamline CHV forcewake stuff
Date: Mon, 5 May 2014 18:17:34 +0530 [thread overview]
Message-ID: <1399294059-20748-6-git-send-email-deepak.s@linux.intel.com> (raw)
In-Reply-To: <1399294059-20748-1-git-send-email-deepak.s@linux.intel.com>
From: Deepak S <deepak.s@linux.intel.com>
Streamline the CHV forcewake functions just like was done for VLV.
This will also fix a bug in accessing the common well registers,
where we'd end up trying to wake up the wells too many times
since we'd call force_wake_get/put twice per register access, with
FORCEFAKE_ALL both times.
v2: Re-factor CHV/VLV Forcewake offsets (Ben)
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 148 ++++++++++++++++--------------------
1 file changed, 66 insertions(+), 82 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 4f1f199..d1a8c72 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -484,41 +484,43 @@ void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
#define NEEDS_FORCE_WAKE(dev_priv, reg) \
((reg) < 0x40000 && (reg) != FORCEWAKE)
+#define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
+
#define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
- (((reg) >= 0x2000 && (reg) < 0x4000) ||\
- ((reg) >= 0x5000 && (reg) < 0x8000) ||\
- ((reg) >= 0xB000 && (reg) < 0x12000) ||\
- ((reg) >= 0x2E000 && (reg) < 0x30000))
+ (REG_RANGE((reg), 0x2000, 0x4000) || \
+ REG_RANGE((reg), 0x5000, 0x8000) || \
+ REG_RANGE((reg), 0xB000, 0x12000) || \
+ REG_RANGE((reg), 0x2E000, 0x30000))
-#define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\
- (((reg) >= 0x12000 && (reg) < 0x14000) ||\
- ((reg) >= 0x22000 && (reg) < 0x24000) ||\
- ((reg) >= 0x30000 && (reg) < 0x40000))
+#define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
+ (REG_RANGE((reg), 0x12000, 0x14000) || \
+ REG_RANGE((reg), 0x22000, 0x24000) || \
+ REG_RANGE((reg), 0x30000, 0x40000))
#define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
- (((reg) >= 0x2000 && (reg) < 0x4000) ||\
- ((reg) >= 0x5000 && (reg) < 0x8000) ||\
- ((reg) >= 0x8300 && (reg) < 0x8500) ||\
- ((reg) >= 0xB000 && (reg) < 0xC000) ||\
- ((reg) >= 0xE000 && (reg) < 0xE800))
-
-#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)\
- (((reg) >= 0x8800 && (reg) < 0x8900) ||\
- ((reg) >= 0xD000 && (reg) < 0xD800) ||\
- ((reg) >= 0x12000 && (reg) < 0x14000) ||\
- ((reg) >= 0x1A000 && (reg) < 0x1C000) ||\
- ((reg) >= 0x1E800 && (reg) < 0x1EA00) ||\
- ((reg) >= 0x30000 && (reg) < 0x40000))
-
-#define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)\
- (((reg) >= 0x4000 && (reg) < 0x5000) ||\
- ((reg) >= 0x8000 && (reg) < 0x8300) ||\
- ((reg) >= 0x8500 && (reg) < 0x8600) ||\
- ((reg) >= 0x9000 && (reg) < 0xB000) ||\
- ((reg) >= 0xC000 && (reg) < 0xc800) ||\
- ((reg) >= 0xF000 && (reg) < 0x10000) ||\
- ((reg) >= 0x14000 && (reg) < 0x14400) ||\
- ((reg) >= 0x22000 && (reg) < 0x24000))
+ (REG_RANGE((reg), 0x2000, 0x4000) || \
+ REG_RANGE((reg), 0x5000, 0x8000) || \
+ REG_RANGE((reg), 0x8300, 0x8500) || \
+ REG_RANGE((reg), 0xB000, 0xC000) || \
+ REG_RANGE((reg), 0xE000, 0xE800))
+
+#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
+ (REG_RANGE((reg), 0x8800, 0x8900) || \
+ REG_RANGE((reg), 0xD000, 0xD800) || \
+ REG_RANGE((reg), 0x12000, 0x14000) || \
+ REG_RANGE((reg), 0x1A000, 0x1C000) || \
+ REG_RANGE((reg), 0x1E800, 0x1EA00) || \
+ REG_RANGE((reg), 0x30000, 0x40000))
+
+#define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
+ (REG_RANGE((reg), 0x4000, 0x5000) || \
+ REG_RANGE((reg), 0x8000, 0x8300) || \
+ REG_RANGE((reg), 0x8500, 0x8600) || \
+ REG_RANGE((reg), 0x9000, 0xB000) || \
+ REG_RANGE((reg), 0xC000, 0xC800) || \
+ REG_RANGE((reg), 0xF000, 0x10000) || \
+ REG_RANGE((reg), 0x14000, 0x14400) || \
+ REG_RANGE((reg), 0x22000, 0x24000))
static void
ilk_dummy_write(struct drm_i915_private *dev_priv)
@@ -618,33 +620,23 @@ static u##x \
chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
unsigned fwengine = 0; \
REG_READ_HEADER(x); \
- if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
- fwengine = FORCEWAKE_RENDER; \
- else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
- fwengine = FORCEWAKE_MEDIA; \
- else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
- fwengine = FORCEWAKE_ALL; \
- if (FORCEWAKE_RENDER & fwengine) { \
- if (dev_priv->uncore.fw_rendercount++ == 0) \
- (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
- fwengine); \
- } \
- if (FORCEWAKE_MEDIA & fwengine) { \
- if (dev_priv->uncore.fw_mediacount++ == 0) \
- (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
- fwengine); \
+ if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
+ if (dev_priv->uncore.fw_rendercount == 0) \
+ fwengine = FORCEWAKE_RENDER; \
+ } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
+ if (dev_priv->uncore.fw_mediacount == 0) \
+ fwengine = FORCEWAKE_MEDIA; \
+ } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
+ if (dev_priv->uncore.fw_rendercount == 0) \
+ fwengine |= FORCEWAKE_RENDER; \
+ if (dev_priv->uncore.fw_mediacount == 0) \
+ fwengine |= FORCEWAKE_MEDIA; \
} \
+ if (fwengine) \
+ dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
val = __raw_i915_read##x(dev_priv, reg); \
- if (FORCEWAKE_RENDER & fwengine) { \
- if (--dev_priv->uncore.fw_rendercount == 0) \
- (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
- fwengine); \
- } \
- if (FORCEWAKE_MEDIA & fwengine) { \
- if (--dev_priv->uncore.fw_mediacount == 0) \
- (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
- fwengine); \
- } \
+ if (fwengine) \
+ dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
REG_READ_FOOTER; \
}
@@ -778,35 +770,27 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
static void \
chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
unsigned fwengine = 0; \
- bool __needs_put = !is_gen8_shadowed(dev_priv, reg); \
+ bool shadowed = is_gen8_shadowed(dev_priv, reg); \
REG_WRITE_HEADER; \
- if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
- fwengine = FORCEWAKE_RENDER; \
- else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
- fwengine = FORCEWAKE_MEDIA; \
- else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
- fwengine = FORCEWAKE_ALL; \
- if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \
- if (dev_priv->uncore.fw_rendercount++ == 0) \
- (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
- fwengine); \
- } \
- if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \
- if (dev_priv->uncore.fw_mediacount++ == 0) \
- (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
- fwengine); \
+ if (!shadowed) { \
+ if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
+ if (dev_priv->uncore.fw_rendercount == 0) \
+ fwengine = FORCEWAKE_RENDER; \
+ } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
+ if (dev_priv->uncore.fw_mediacount == 0) \
+ fwengine = FORCEWAKE_MEDIA; \
+ } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
+ if (dev_priv->uncore.fw_rendercount == 0) \
+ fwengine |= FORCEWAKE_RENDER; \
+ if (dev_priv->uncore.fw_mediacount == 0) \
+ fwengine |= FORCEWAKE_MEDIA; \
+ } \
} \
+ if (fwengine) \
+ dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
__raw_i915_write##x(dev_priv, reg, val); \
- if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \
- if (--dev_priv->uncore.fw_rendercount == 0) \
- (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
- fwengine); \
- } \
- if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \
- if (--dev_priv->uncore.fw_mediacount == 0) \
- (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
- fwengine); \
- } \
+ if (fwengine) \
+ dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
REG_WRITE_FOOTER; \
}
--
1.9.1
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next prev parent reply other threads:[~2014-05-05 12:47 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-05 12:47 [PATCH 00/10] Enable RC6/Turbo on CHV deepak.s
2014-05-05 12:47 ` [PATCH 01/10] drm/i915/bdw: Implement a basic PM interrupt handler deepak.s
2014-05-07 13:58 ` Ville Syrjälä
2014-05-05 12:47 ` [PATCH 02/10] drm/i915: Enable PM Interrupts target via Display Interface deepak.s
2014-05-07 14:08 ` Ville Syrjälä
2014-05-14 15:37 ` [PATCH v3] " deepak.s
2014-05-14 15:47 ` Ville Syrjälä
2014-05-05 12:47 ` [PATCH 03/10] drm/i915/chv: Enable Render Standby (RC6) for Cherryview deepak.s
2014-05-09 13:19 ` Mika Kuoppala
2014-05-14 15:47 ` Deepak S
2014-05-15 9:57 ` [PATCH v5] " deepak.s
2014-05-15 10:00 ` Deepak S
2014-05-15 10:16 ` Mika Kuoppala
2014-05-15 10:22 ` Mika Kuoppala
2014-05-15 12:38 ` [PATCH v5 1/8] " deepak.s
2014-05-05 12:47 ` [PATCH 04/10] drm/i915/chv: Added CHV specific register read and write deepak.s
2014-05-16 14:46 ` Mika Kuoppala
2014-05-05 12:47 ` deepak.s [this message]
2014-05-05 12:47 ` [PATCH 06/10] drm/i915/chv: Enable RPS (Turbo) for Cherryview deepak.s
2014-05-05 12:47 ` [PATCH 07/10] drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0 deepak.s
2014-05-05 12:47 ` [PATCH 08/10] drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV deepak.s
2014-05-05 12:47 ` [PATCH 09/10] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating deepak.s
2014-05-05 12:47 ` [PATCH 10/10] drm/i915/chv: Freq(opcode) request for CHV deepak.s
2014-05-07 14:23 ` Ville Syrjälä
2014-05-12 13:53 ` [PATCH v2] " deepak.s
2014-05-15 21:22 ` [PATCH 00/10] Enable RC6/Turbo on CHV Daniel Vetter
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