From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 17/71] drm/i915/chv: Update Cherryview DPLL changes to support Port D. v2 Date: Mon, 12 May 2014 14:29:18 +0300 Message-ID: <1399894158.4454.4.camel@intelbox> References: <1397039349-10639-1-git-send-email-ville.syrjala@linux.intel.com> <1397039349-10639-18-git-send-email-ville.syrjala@linux.intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0106177213==" Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id A8B416E481 for ; Mon, 12 May 2014 04:29:30 -0700 (PDT) In-Reply-To: <1397039349-10639-18-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0106177213== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-tGwyz9STP0+K4ZauBApw" --=-tGwyz9STP0+K4ZauBApw Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 2014-04-09 at 13:28 +0300, ville.syrjala@linux.intel.com wrote: > From: Chon Ming Lee >=20 > The additional DPLL registers added to support Port D. Besides, add > some new PHY control and status registers based on B-spec. >=20 > v2: Based on Ville review > - Corrected DPIO_PHY_STATUS offset and name. > - Rebase based on upstream change after introduce enum dpio_phy and > enum dpio_channel. >=20 > v3: Rebased on top of Antti's 3-pipe prep patch. Note that the new offset= s for > the DPLL registers aren't in place yet, so this introduces a slight regre= ssion. > But since 3 pipe support isn't fully enabled yet anyaway in -internal thi= s > shouldn't matter too much. >=20 > Signed-off-by: Chon Ming Lee > --- > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ > drivers/gpu/drm/i915/intel_display.c | 11 +++++++++-- > drivers/gpu/drm/i915/intel_drv.h | 1 + > 3 files changed, 16 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index beb04ab..8aea092 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -29,6 +29,8 @@ > #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a))) > =20 > #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) > +#define _PIPE3(pipe, a, b, c) (pipe < 2 ? _PIPE(pipe, a, b) : c) > +#define _PORT3(port, a, b, c) (port < 2 ? _PORT(port, a, b) : c) These could go to patch 71, where they're first used. Either way: Reviewed-by: Imre Deak > =20 > #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a)) > #define _MASKED_BIT_DISABLE(a) ((a) << 16) > @@ -1385,6 +1387,10 @@ enum punit_power_well { > #define DPLL_PORTB_READY_MASK (0xf) > =20 > #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 > + > +/* Additional CHV pll/phy registers */ > +#define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240) > +#define DPLL_PORTD_READY_MASK (0xf) > /* > * The i830 generation, in LVDS mode, defines P1 as the bit number set w= ithin > * this field (only one bit may be set). > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index df6732e..153f244 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1535,21 +1535,28 @@ void vlv_wait_port_ready(struct drm_i915_private = *dev_priv, > struct intel_digital_port *dport) > { > u32 port_mask; > + int dpll_reg; > =20 > switch (dport->port) { > case PORT_B: > port_mask =3D DPLL_PORTB_READY_MASK; > + dpll_reg =3D DPLL(0); > break; > case PORT_C: > port_mask =3D DPLL_PORTC_READY_MASK; > + dpll_reg =3D DPLL(0); > + break; > + case PORT_D: > + port_mask =3D DPLL_PORTD_READY_MASK; > + dpll_reg =3D DPIO_PHY_STATUS; > break; > default: > BUG(); > } > =20 > - if (wait_for((I915_READ(DPLL(0)) & port_mask) =3D=3D 0, 1000)) > + if (wait_for((I915_READ(dpll_reg) & port_mask) =3D=3D 0, 1000)) > WARN(1, "timed out waiting for port %c ready: 0x%08x\n", > - port_name(dport->port), I915_READ(DPLL(0))); > + port_name(dport->port), I915_READ(dpll_reg)); > } > =20 > /** > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/inte= l_drv.h > index 9002e77..087e471 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -535,6 +535,7 @@ vlv_dport_to_channel(struct intel_digital_port *dport= ) > { > switch (dport->port) { > case PORT_B: > + case PORT_D: > return DPIO_CH0; > case PORT_C: > return DPIO_CH1; --=-tGwyz9STP0+K4ZauBApw Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJTcLCOAAoJEORIIAnNuWDF6jwIANHlpsI/3LTtzCqnPuXjO4qQ OsmBamRqdYv95KHaQKDV1tckRbNlAspML2/LFJEDa4w5us0shKUx5EtdFlJllETP 58ZswJUK3g6/X5v/VipzyvT/PZctMTpTnbDvQpOTFJqizXW5iTnBdqza4N2CSHl6 yIC1dk7m/vsxOwQEXaM6iUB5I67f9G++4O/EriQBScHt2D852CV2+GxvuVhHKhYr 0sgMxI3hKyPzZGV/QwfdffXd8fol6HdHLhZh2JkaawWO2Cvz5ks2hUwGp1mt6o0x pafUF+VTs3z+XndT0nbbZhVqlQ5+DERTw1n7xerW9Fy+TXmRes7qHIdR1U1OOb4= =znmX -----END PGP SIGNATURE----- --=-tGwyz9STP0+K4ZauBApw-- --===============0106177213== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0106177213==--