From: deepak.s@linux.intel.com
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 6/7] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating
Date: Fri, 23 May 2014 21:00:20 +0530 [thread overview]
Message-ID: <1400859021-32202-7-git-send-email-deepak.s@linux.intel.com> (raw)
In-Reply-To: <1400859021-32202-1-git-send-email-deepak.s@linux.intel.com>
From: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
[vsyrjala: Fix merge fubmle where the code ended up in
g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 08dcdc5..0b73a6d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4026,7 +4026,18 @@ static void cherryview_enable_rps(struct drm_device *dev)
GEN6_RP_UP_BUSY_AVG |
GEN6_RP_DOWN_IDLE_AVG);
+ /* ToDo: Update the mem freq based on latest spec [CHV]*/
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+ switch ((val >> 6) & 3) {
+ case 0:
+ case 1:
+ case 2:
+ dev_priv->mem_freq = 1600;
+ break;
+ case 3:
+ dev_priv->mem_freq = 2000;
+ break;
+ }
DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
--
1.9.1
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next prev parent reply other threads:[~2014-05-23 15:30 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-23 15:30 [PATCH 0/7] Enable RC6/Turbo on CHV deepak.s
2014-05-23 15:30 ` [PATCH 1/7] drm/i915/chv: Enable Render Standby (RC6) for Cherryview deepak.s
2014-05-23 15:30 ` [PATCH 2/7] drm/i915/chv: Added CHV specific register read and write and Streamline CHV forcewake stuff deepak.s
2014-05-26 8:07 ` Daniel Vetter
2014-05-23 15:30 ` [PATCH 3/7] drm/i915/chv: Enable RPS (Turbo) for Cherryview deepak.s
2014-05-26 13:30 ` Mika Kuoppala
2014-05-26 13:54 ` Deepak S
2014-05-26 14:32 ` Ville Syrjälä
2014-05-27 3:29 ` Deepak S
2014-05-26 14:37 ` Mika Kuoppala
2014-05-27 3:29 ` Deepak S
2014-05-27 6:36 ` [PATCH v6] " deepak.s
2014-05-27 10:29 ` [PATCH v7] " deepak.s
2014-05-27 10:45 ` Mika Kuoppala
2014-05-27 11:44 ` Daniel Vetter
2014-05-23 15:30 ` [PATCH 4/7] drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0 deepak.s
2014-05-23 15:30 ` [PATCH 5/7] drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV deepak.s
2014-05-23 15:30 ` deepak.s [this message]
2014-05-26 15:19 ` [PATCH 6/7] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating Mika Kuoppala
2014-05-27 11:42 ` Daniel Vetter
2014-05-27 11:59 ` Ville Syrjälä
2014-05-27 12:11 ` Deepak S
2014-05-27 12:13 ` Deepak S
2014-05-23 15:30 ` [PATCH 7/7] drm/i915/chv: Freq(opcode) request for CHV deepak.s
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