From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: [PATCH 3/6] drm/i915/vlv: move CRI refclk enable into __vlv_set_power_well Date: Fri, 23 May 2014 13:16:42 -0700 Message-ID: <1400876205-12997-3-git-send-email-jbarnes@virtuousgeek.org> References: <1400876205-12997-1-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from gproxy4-pub.mail.unifiedlayer.com (gproxy4-pub.mail.unifiedlayer.com [69.89.23.142]) by gabe.freedesktop.org (Postfix) with SMTP id 4B7BC6E1F7 for ; Fri, 23 May 2014 13:16:57 -0700 (PDT) Received: from [67.161.37.189] (port=49075 helo=localhost.localdomain) by box514.bluehost.com with esmtpsa (TLSv1.2:DHE-RSA-AES256-GCM-SHA384:256) (Exim 4.82) (envelope-from ) id 1Wnvtb-0000KX-H6 for intel-gfx@lists.freedesktop.org; Fri, 23 May 2014 14:16:51 -0600 In-Reply-To: <1400876205-12997-1-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org This needs to be done before we power back on the CMN_BC well so the PHY can calibrate properly. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 8 -------- drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++ 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index bdb4624..369cd1e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1477,14 +1477,6 @@ static void intel_reset_dpio(struct drm_device *dev) if (!IS_VALLEYVIEW(dev)) return; - /* - * Enable the CRI clock source so we can get at the display and the - * reference clock for VGA hotplug / manual detection. - */ - I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | - DPLL_REFA_CLK_ENABLE_VLV | - DPLL_INTEGRATED_CRI_CLK_VLV); - if (IS_CHERRYVIEW(dev)) { enum dpio_phy phy; u32 val; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 8f7dbb9..e8f0c85 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5731,6 +5731,17 @@ void __vlv_set_power_well(struct drm_i915_private *dev_priv, u32 state; u32 ctrl; + if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC && enable) { + /* + * Enable the CRI clock source so we can get at the display + * and the reference clock for VGA hotplug / manual detection. + */ + I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | + DPLL_REFA_CLK_ENABLE_VLV | + DPLL_INTEGRATED_CRI_CLK_VLV); + udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ + } + mask = PUNIT_PWRGT_MASK(power_well_id); state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : PUNIT_PWRGT_PWR_GATE(power_well_id); -- 1.8.4.2