From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH] drm/i915: dsi: fix pipe-off timeout due to port vs. pipe disable ordering Date: Tue, 27 May 2014 18:12:30 +0300 Message-ID: <1401203550.10798.61.camel@intelbox> References: <1401196539-17715-1-git-send-email-imre.deak@intel.com> <53849DF7.4040403@intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0940767257==" Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 1ABCF6E729 for ; Tue, 27 May 2014 08:12:43 -0700 (PDT) In-Reply-To: <53849DF7.4040403@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "Kumar, Shobhit" Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0940767257== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-a4tdWj418mVAtK35FiNi" --=-a4tdWj418mVAtK35FiNi Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, 2014-05-27 at 19:45 +0530, Kumar, Shobhit wrote: > On 5/27/2014 6:45 PM, Imre Deak wrote: > > If we disable first the port (by disabling DPI) and only then the > > display pipe the pipe-off flag will never be set, possibly leading to a > > hanged pipe state at the next modeset-enable. > > > > Note that according to the VLV2 display cluster HAS, we should disable > > the port before the pipe. This doesn't seem to match reality based on > > the above and it's also asymmetric with the enabling sequence, where we > > first enable the port and then the pipe. > > > > Signed-off-by: Imre Deak > > --- > > drivers/gpu/drm/i915/intel_dsi.c | 9 ++++++++- > > 1 file changed, 8 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/in= tel_dsi.c > > index e73bec6..3756af1 100644 > > --- a/drivers/gpu/drm/i915/intel_dsi.c > > +++ b/drivers/gpu/drm/i915/intel_dsi.c > > @@ -206,6 +206,11 @@ static void intel_dsi_enable_nop(struct intel_enco= der *encoder) > > */ > > } > > > > +static void intel_dsi_disable_nop(struct intel_encoder *encoder) > > +{ > > + DRM_DEBUG_KMS("\n"); > > +} > > + >=20 > Make this as *_pre_disable and the SHUTDOWN command should be sent in=20 > this function. That is the recommended sequence in disable path. First= =20 > thing is to shutdown the panel. Remove that bit from the intel_dsi_disabl= e. I tried this, but it results in a "Timeout waiting for DPI FIFO empty" error when sending the SHUTDOWN command. This order would be also asymmetric with the enabling sequence where we first turn on the panel and only then enable the pipe. So I would need more explanation for the above before moving the SHUTDOWN command earlier. --Imre=20 > > static void intel_dsi_disable(struct intel_encoder *encoder) > > { > > struct drm_device *dev =3D encoder->base.dev; > > @@ -293,6 +298,8 @@ static void intel_dsi_post_disable(struct intel_enc= oder *encoder) > > > > DRM_DEBUG_KMS("\n"); > > > > + intel_dsi_disable(encoder); > > + > > intel_dsi_clear_device_ready(encoder); > > > > val =3D I915_READ(DSPCLK_GATE_D); > > @@ -691,7 +698,7 @@ bool intel_dsi_init(struct drm_device *dev) > > intel_encoder->pre_pll_enable =3D intel_dsi_pre_pll_enable; > > intel_encoder->pre_enable =3D intel_dsi_pre_enable; > > intel_encoder->enable =3D intel_dsi_enable_nop; > > - intel_encoder->disable =3D intel_dsi_disable; > > + intel_encoder->disable =3D intel_dsi_disable_nop; >=20 > intel_encoder->disable =3D intel_dsi_pre_disable > as suggested above >=20 > > intel_encoder->post_disable =3D intel_dsi_post_disable; > > intel_encoder->get_hw_state =3D intel_dsi_get_hw_state; > > intel_encoder->get_config =3D intel_dsi_get_config; > > >=20 > Regards > Shobhit --=-a4tdWj418mVAtK35FiNi Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJThKteAAoJEORIIAnNuWDF4DUH/1EW9mbheiawsEEYTPvgJZlK Tb1/85ErEzQ/zbIjBLDrz4Dfof30kteLVbVDD0nTCKeUbw4RMbY5kxJlHKDxXlv9 DiwMFIk/EcjculbTpyhNg0Zo0E87pcJhebzpk28cEy+xBzxogujSvSvWbYaDBGZk O8yGVHCyHqZZWNNVxobpoETEz5HS/ucGhTYRCk9GI1UBaW/iJdUfsLIYtkj8bnXT ZnbCRzcmFCxsPxpL40oIe8nwFC/39WWoWhKNGcqERmJUTvyBrpvPZ/T4jOqcSFTJ 5d5FpHdmuyErdVeqCyfeqHNgvu3+l3F1CArJO5xqDUkURC5o+qJvlQJurQsepJ4= =rNY4 -----END PGP SIGNATURE----- --=-a4tdWj418mVAtK35FiNi-- --===============0940767257== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0940767257==--