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From: Imre Deak <imre.deak@intel.com>
To: sagar.a.kamble@intel.com
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>,
	intel-gfx@lists.freedesktop.org, shashidhar.hiremath@intel.com
Subject: Re: [PATCH 1/2] drm/i915: do runtime_get/put during display well power gate/ungate
Date: Tue, 10 Jun 2014 15:24:34 +0300	[thread overview]
Message-ID: <1402403074.7876.51.camel@intelbox> (raw)
In-Reply-To: <1402340250-3909-2-git-send-email-sagar.a.kamble@intel.com>


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Hi Sagar,

On Tue, 2014-06-10 at 00:27 +0530, sagar.a.kamble@intel.com wrote:
> From: Sagar Kamble <sagar.a.kamble@intel.com>
> 
> Display power island is on during boot, we have one count for it
> once this power gates, we do a put making sure runtime_suspend is
> called
> 
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> (supporter:INTEL DRM DRIVERS...)
> Cc: Jani Nikula <jani.nikula@linux.intel.com> (supporter:INTEL DRM DRIVERS...)
> Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f83d1ff..b333aae 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6017,6 +6017,12 @@ void __vlv_set_power_well(struct drm_i915_private *dev_priv,
>  			  state,
>  			  vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
>  
> +	if (PUNIT_POWER_WELL_DISP2D == power_well_id) {
> +		if (enable)
> +			intel_runtime_pm_get(dev_priv);
> +		else
> +			intel_runtime_pm_put(dev_priv);
> +	}

The RPM refcount should already be get/put properly in
intel_display_power_get/put(), so the above doesn't seem correct to me.

With current -nightly after blanking the screen the RPM refcount does
drop to 0 for me, so I'm not sure what you're missing. One possibility
is:

# echo auto > /sys/bus/pci/devices/0000:00:02.0/power/control

--Imre


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  reply	other threads:[~2014-06-10 12:24 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-09 18:57 [PATCH 0/2] Enabling D0i3 transition for Valleyview sagar.a.kamble
2014-06-09 18:57 ` [PATCH 1/2] drm/i915: do runtime_get/put during display well power gate/ungate sagar.a.kamble
2014-06-10 12:24   ` Imre Deak [this message]
2014-06-09 18:57 ` [PATCH 2/2] drm/i915/vlv: Set D3_hot for vlv during runtime_suspend sagar.a.kamble
2014-06-10 12:43   ` Imre Deak
2014-06-10 17:35     ` Sagar Arun Kamble
2014-06-10 17:51       ` Imre Deak
2014-06-11  8:23         ` Sagar Arun Kamble
2014-06-11 10:17           ` Daniel Vetter
2014-06-11 10:49             ` Sagar Arun Kamble

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