From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 2/2] drm/i915/vlv: Set D3_hot for vlv during runtime_suspend Date: Tue, 10 Jun 2014 15:43:03 +0300 Message-ID: <1402404183.7876.67.camel@intelbox> References: <1402340250-3909-1-git-send-email-sagar.a.kamble@intel.com> <1402340250-3909-3-git-send-email-sagar.a.kamble@intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0466600825==" Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id ADD266E025 for ; Tue, 10 Jun 2014 05:43:15 -0700 (PDT) In-Reply-To: <1402340250-3909-3-git-send-email-sagar.a.kamble@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: sagar.a.kamble@intel.com Cc: Daniel Vetter , intel-gfx@lists.freedesktop.org, shashidhar.hiremath@intel.com List-Id: intel-gfx@lists.freedesktop.org --===============0466600825== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-tCl8OdMVGVg51Q5LwXZ2" --=-tCl8OdMVGVg51Q5LwXZ2 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, 2014-06-10 at 00:27 +0530, sagar.a.kamble@intel.com wrote: > From: Sagar Kamble >=20 > To do a platform wide S0i3 transition, Gfx is required to go > to D3_hot state. pci_save_state and pci_restore_state needed to avoid rin= g > hangs across D3_hot transitions. >=20 > Cc: Daniel Vetter (supporter:INTEL DRM DRIVERS..= .) > Cc: Jani Nikula (supporter:INTEL DRM DRIVER= S...) > Signed-off-by: Sagar Kamble > --- > drivers/gpu/drm/i915/i915_drv.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) >=20 > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_= drv.c > index 5a08c86..70bb456 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -1412,6 +1412,11 @@ static int intel_runtime_suspend(struct device *de= vice) > * via the suspend path. > */ > intel_opregion_notify_adapter(dev, PCI_D1); > + if (IS_VALLEYVIEW(dev)) { > + pci_save_state(pdev); > + pci_disable_device(pdev); > + pci_set_power_state(pdev, PCI_D3hot); > + } > =20 > DRM_DEBUG_KMS("Device suspended\n"); > return 0; > @@ -1428,6 +1433,12 @@ static int intel_runtime_resume(struct device *dev= ice) > =20 > DRM_DEBUG_KMS("Resuming device\n"); > =20 > + if (IS_VALLEYVIEW(dev)) { > + pci_set_power_state(pdev, PCI_D0); > + pci_restore_state(pdev); > + pci_enable_device(pdev); > + } Setting the proper Dx state and saving/restoring the PCI config space is already done for us by the PCI runtime PM framework, see pci_pm_runtime_suspend/resume(). They don't disable/enable the PCI device, but I'm not sure if that's really needed. Based on the docs I found so far the requirement for S0ix is that we put the device into D3 state and that's already the case w/o disabling the device. So could you explain/confirm if we need that particular step? Also if it's really needed it should be done for all platforms. --Imre=20 > + > intel_opregion_notify_adapter(dev, PCI_D0); > dev_priv->pm.suspended =3D false; > =20 --=-tCl8OdMVGVg51Q5LwXZ2 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJTlv1XAAoJEORIIAnNuWDFK04IAISLipI6OSHO6MU4G1M7/dOn KuFqkFZfsCKvjyjSwZXCMdxr5u20PTJ0+pI4hKDXu4NvLaZnOlDqaUgk4MnLtbph ++Sqx4Br/3cwFNFgKvN0kSgOI5G6ayg9x9fOb2rBmc6MdqNMppJfpDUgN8XuJLIk pAo1ibny4CvDcru+K6aff0VclJIzq8DryPFtc4U5vhBo+P7dTmepFEh4cthdnCk7 H32ZHcYdfzKl2Of7O/vAMliWRlwic4c1Q7M8fPhkOJUvcwK2pIkzJ3Kv92zUGON/ p1j7+uu9HxkOgmhRtHjXG+FJcTSIm2VmIHiIpABVF2Pnovb0hzraam8F1H7eyjo= =xJIn -----END PGP SIGNATURE----- --=-tCl8OdMVGVg51Q5LwXZ2-- --===============0466600825== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0466600825==--