From mboxrd@z Thu Jan 1 00:00:00 1970 From: deepak.s@linux.intel.com Subject: [PATCH] drm/i915: Drop WA to fix Voltage not getting dropped to Vmin when Gfx is power gated. Date: Fri, 13 Jun 2014 15:46:14 +0530 Message-ID: <1402654574-5287-1-git-send-email-deepak.s@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 151EF6E163 for ; Fri, 13 Jun 2014 03:16:41 -0700 (PDT) List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org From: Deepak S Workaround fixed in BYT. Forcing Gfx clk up not needed, and Requesting the min freq should bring bring the voltage Vnn. Signed-off-by: Deepak S --- drivers/gpu/drm/i915/intel_pm.c | 40 +--------------------------------------- 1 file changed, 1 insertion(+), 39 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 0b088fe..9aee28b 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3198,44 +3198,6 @@ void gen6_set_rps(struct drm_device *dev, u8 val) trace_intel_gpu_freq_change(val * 50); } -/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down - * - * * If Gfx is Idle, then - * 1. Mask Turbo interrupts - * 2. Bring up Gfx clock - * 3. Change the freq to Rpn and wait till P-Unit updates freq - * 4. Clear the Force GFX CLK ON bit so that Gfx can down - * 5. Unmask Turbo interrupts -*/ -static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) -{ - /* - * When we are idle. Drop to min voltage state. - */ - - if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit) - return; - - /* Mask turbo interrupt so that they will not come in between */ - I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); - - vlv_force_gfx_clock(dev_priv, true); - - dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit; - - vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, - dev_priv->rps.min_freq_softlimit); - - if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) - & GENFREQSTATUS) == 0, 5)) - DRM_ERROR("timed out waiting for Punit\n"); - - vlv_force_gfx_clock(dev_priv, false); - - I915_WRITE(GEN6_PMINTRMSK, - gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); -} - void gen6_rps_idle(struct drm_i915_private *dev_priv) { struct drm_device *dev = dev_priv->dev; @@ -3243,7 +3205,7 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv) mutex_lock(&dev_priv->rps.hw_lock); if (dev_priv->rps.enabled) { if (IS_VALLEYVIEW(dev)) - vlv_set_rps_idle(dev_priv); + valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); else gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); dev_priv->rps.last_adj = 0; -- 1.9.1