From mboxrd@z Thu Jan 1 00:00:00 1970 From: oscar.mateo@intel.com Subject: [PATCH 4/4] drm/i915/chv: Ack interrupts before handling them (CHV) Date: Mon, 16 Jun 2014 12:30:29 +0100 Message-ID: <1402918229-7246-4-git-send-email-oscar.mateo@intel.com> References: <1402918229-7246-1-git-send-email-oscar.mateo@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 31B056E4D6 for ; Mon, 16 Jun 2014 04:35:01 -0700 (PDT) In-Reply-To: <1402918229-7246-1-git-send-email-oscar.mateo@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org From: Oscar Mateo Otherwise, we might receive a new interrupt before we have time to ack the first one, eventually missing it. Notice that, before clearing a port-sourced interrupt in the IIR, the corresponding interrupt source status in the PORT_HOTPLUG_STAT must be cleared. Spotted by Bob Beckett . Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/i915_irq.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 59ff177..98009b5 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1895,21 +1895,22 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg) if (master_ctl == 0 && iir == 0) break; - I915_WRITE(GEN8_MASTER_IRQ, 0); - - gen8_gt_irq_handler(dev, dev_priv, master_ctl); + ret = IRQ_HANDLED; - valleyview_pipestat_irq_handler(dev, iir); + I915_WRITE(GEN8_MASTER_IRQ, 0); - /* Consume port. Then clear IIR or we'll miss events */ - i9xx_hpd_irq_handler(dev); + if (iir) { + /* Consume port. Then clear IIR or we'll miss events */ + if (iir & I915_DISPLAY_PORT_INTERRUPT) + i9xx_hpd_irq_handler(dev); + I915_WRITE(VLV_IIR, iir); + valleyview_pipestat_irq_handler(dev, iir); + } - I915_WRITE(VLV_IIR, iir); + gen8_gt_irq_handler(dev, dev_priv, master_ctl); I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); POSTING_READ(GEN8_MASTER_IRQ); - - ret = IRQ_HANDLED; } return ret; -- 1.9.0