From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: [PATCH 2/2] drm/i915: fix VDD state tracking after system resume Date: Fri, 27 Jun 2014 21:35:14 +0300 Message-ID: <1403894114-28007-2-git-send-email-imre.deak@intel.com> References: <1403894114-28007-1-git-send-email-imre.deak@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 378896E0F0 for ; Fri, 27 Jun 2014 11:35:37 -0700 (PDT) In-Reply-To: <1403894114-28007-1-git-send-email-imre.deak@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org Just like during booting the BIOS can leave the VDD bit enabled after system resume. So apply the same state sanitization there too. This fixes a problem where after resume the port power domain refcount gets unbalanced. Reported-by: Jarkko Nikula Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/intel_display.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 065984d..8989069 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12875,6 +12875,12 @@ void intel_modeset_setup_hw_state(struct drm_device *dev, /* HW state is read out, now we need to sanitize this mess. */ list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { + /* + * Do the following only during resume, since at driver + * loading it's done early when initializing the encoder. + */ + if (force_restore) + intel_edp_panel_vdd_sanitize(encoder); intel_sanitize_encoder(encoder); } -- 1.8.4