From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rodrigo Vivi Subject: [PATCH 01/10] drm/i915: Bring UP Power Wells before disabling RC6. Date: Thu, 3 Jul 2014 17:32:57 -0400 Message-ID: <1404423186-2019-2-git-send-email-rodrigo.vivi@intel.com> References: <1404423186-2019-1-git-send-email-rodrigo.vivi@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-pa0-f46.google.com (mail-pa0-f46.google.com [209.85.220.46]) by gabe.freedesktop.org (Postfix) with ESMTP id 04BE56E77A for ; Thu, 3 Jul 2014 14:33:13 -0700 (PDT) Received: by mail-pa0-f46.google.com with SMTP id eu11so852266pac.5 for ; Thu, 03 Jul 2014 14:33:12 -0700 (PDT) In-Reply-To: <1404423186-2019-1-git-send-email-rodrigo.vivi@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org Cc: Deepak S , Paulo Zanoni , Rodrigo Vivi List-Id: intel-gfx@lists.freedesktop.org From: Deepak S We need do forcewake before Disabling RC6, This is what the BIOS expects while going into suspend. v2: updated commit message. (Daniel) Reviewer: Paulo Zanoni Cc: Paulo Zanoni Signed-off-by: Deepak S Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_pm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d771e82..1e4611a 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3354,8 +3354,14 @@ static void valleyview_disable_rps(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; + /* we're doing forcewake before Disabling RC6, + * This what the BIOS expects when going into suspend */ + gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); + I915_WRITE(GEN6_RC_CONTROL, 0); + gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); + gen6_disable_rps_interrupts(dev); } -- 1.9.0