From mboxrd@z Thu Jan 1 00:00:00 1970 From: deepak.s@linux.intel.com Subject: [PATCH 5/7] drm/i915: CHV GPU frequency to opcode functions Date: Thu, 10 Jul 2014 13:16:25 +0530 Message-ID: <1404978387-28180-6-git-send-email-deepak.s@linux.intel.com> References: <1404978387-28180-1-git-send-email-deepak.s@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 8DDB58A0BA for ; Wed, 9 Jul 2014 00:51:53 -0700 (PDT) In-Reply-To: <1404978387-28180-1-git-send-email-deepak.s@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org From: Deepak S Adding chv specific fre/encode conversion. Signed-off-by: Deepak S --- drivers/gpu/drm/i915/intel_pm.c | 68 +++++++++++++++++++++++++++++++++++------ 1 file changed, 59 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 6c19ce5..6abd05b 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6975,26 +6975,76 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val) return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6; } -int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) +int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) { - int ret; + int div, freq; - if (!IS_VALLEYVIEW(dev_priv->dev)) + switch (dev_priv->rps.cz_freq) { + case 200: + div = 5; + break; + case 267: + div = 6; + break; + case 320: + case 333: + case 400: + div = 8; + break; + default: return -1; + } - ret = vlv_gpu_freq(dev_priv, val); + freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2); - return ret; + return freq; } -int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) +int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) { - int ret; + int mul, opcode; - if (!IS_VALLEYVIEW(dev_priv->dev)) + switch (dev_priv->rps.cz_freq) { + case 200: + mul = 5; + break; + case 267: + mul = 6; + break; + case 320: + case 333: + case 400: + mul = 8; + break; + default: return -1; + } + + opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2); + + return opcode; +} + +int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) +{ + int ret = -1; + + if (IS_CHERRYVIEW(dev_priv->dev)) + ret = chv_gpu_freq(dev_priv, val); + else if (IS_VALLEYVIEW(dev_priv->dev)) + ret = vlv_gpu_freq(dev_priv, val); + + return ret; +} + +int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) +{ + int ret = -1; - ret = vlv_freq_opcode(dev_priv, val); + if (IS_CHERRYVIEW(dev_priv->dev)) + ret = chv_freq_opcode(dev_priv, val); + else if (IS_VALLEYVIEW(dev_priv->dev)) + ret = vlv_freq_opcode(dev_priv, val); return ret; } -- 1.9.1