From mboxrd@z Thu Jan 1 00:00:00 1970 From: Todd Previte Subject: [PATCH 10/12] drm/i915: Update link training automated test function for Displayport compliance Date: Mon, 14 Jul 2014 12:10:45 -0700 Message-ID: <1405365047-6866-11-git-send-email-tprevite@gmail.com> References: <1405365047-6866-1-git-send-email-tprevite@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-pd0-f171.google.com (mail-pd0-f171.google.com [209.85.192.171]) by gabe.freedesktop.org (Postfix) with ESMTP id 44DDA6E46D for ; Mon, 14 Jul 2014 12:11:35 -0700 (PDT) Received: by mail-pd0-f171.google.com with SMTP id z10so3471993pdj.30 for ; Mon, 14 Jul 2014 12:11:35 -0700 (PDT) In-Reply-To: <1405365047-6866-1-git-send-email-tprevite@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org Implements basic link training functionality for Displayport automated compliance testing. Signed-off-by: Todd Previte --- drivers/gpu/drm/i915/intel_dp.c | 47 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 65830e9..e4b31ad 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3427,6 +3427,53 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) { uint8_t test_result = DP_TEST_NAK; + uint8_t rxdata[2]; + uint8_t link_status[DP_LINK_STATUS_SIZE]; + int bytes_ret = 0; + struct drm_connector *connector = &intel_dp->attached_connector->base; + struct intel_digital_port *intel_dig_port = + enc_to_dig_port(&intel_dp->attached_connector->encoder->base); + + /* Read test parameters */ + bytes_ret = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_LINK_RATE, rxdata, 2); + + /* Set link rate directly */ + intel_dp->link_bw = rxdata[0]; + /* Preserve 7:5 when setting lane count */ + intel_dp->lane_count &= 0xE0; + intel_dp->lane_count |= rxdata[1]; + + DRM_DEBUG_KMS("Displayport: Link training testing - %d lanes @ %02x link rate\n", + intel_dp->lane_count, intel_dp->link_bw); + + /* Train the link */ + intel_dp->DP = intel_dig_port->saved_port_bits | + DDI_BUF_CTL_ENABLE | + DDI_BUF_EMP_400MV_0DB_HSW; + intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); + + if (!intel_dp_start_link_train(intel_dp)) { + DRM_DEBUG_KMS("Displayport: intel_dp_start_link_train() failed\n"); + test_result = false; + } + if (!intel_dp_complete_link_train(intel_dp)) { + DRM_DEBUG_KMS("Displayport: intel_dp_complete_link_train() failed\n"); + test_result = false; + } + if (!intel_dp_stop_link_train(intel_dp)) { + DRM_DEBUG_KMS("Displayport: intel_dp_stop_link_train() failed\n"); + test_result = false; + } + + /* Check link status for successful completion */ + if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) + test_result = true; + + if (test_result == false) { + /* Clear link training here */ + intel_dp_set_idle_link_train(intel_dp); + } + return test_result; } -- 1.9.1