Re: [PATCH 1/5] drm/i915: don't write powered down IRQ registers on Gen 8

Paulo Zanoni
2014-07-10T19:31:53Z

2014-07-08 11:58 GMT-03:00 Daniel Vetter <daniel@ffwll.ch>:
> On Tue, Jul 08, 2014 at 11:15:03AM -0300, Paulo Zanoni wrote:
>> 2014-07-07 18:23 GMT-03:00 Daniel Vetter <daniel@ffwll.ch>:
>> > On Fri, Jul 04, 2014 at 11:50:29AM -0300, Paulo Zanoni wrote:
>> >> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> >>
>> >> If we enable unclaimed register reporting on Gen 8, we will discover
>> >> that the IRQ registers for pipes B and C are also on the power well,
>> >> so writes to them when the power well is disabled result in unclaimed
>> >> register errors.
>> >>
>> >> Also, hsw_power_well_post_enable() already takes care of re-enabling
>> >> them once the power well is enabled.
>> >>
>> >> Testcase: igt/pm_rpm/rte
>> >> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> >
>> > Hm, shouldn't we split this into only setting up pipe A here and the pipe
>> > B stuff once we fire up the power well?
>> >
>>
>> No because these functions might be called when the power wells are
>> already enabled.
>
> Hm, where does this still happen? bdw has power well support and chv has a
> different display block ...

At driver init time... If you load i915.ko and the power wells are
already enabled, we have to do it here.

>
> This code changed too often and I have no idea any more what's up and
> what's down here ;-)
> -Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch

--
Paulo Zanoni