From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 17/40] drm/i915: Add chv cmnlane power wells Date: Fri, 25 Jul 2014 14:55:00 +0300 Message-ID: <1406289300.23035.4.camel@intelbox> References: <1403910271-24984-1-git-send-email-ville.syrjala@linux.intel.com> <1403910271-24984-18-git-send-email-ville.syrjala@linux.intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0201356434==" Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id C39576E80A for ; Fri, 25 Jul 2014 04:55:35 -0700 (PDT) In-Reply-To: <1403910271-24984-18-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0201356434== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-Uda4+EgN6oy3CuDaiUUv" --=-Uda4+EgN6oy3CuDaiUUv Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Sat, 2014-06-28 at 02:04 +0300, ville.syrjala@linux.intel.com wrote: > From: Ville Syrj=C3=A4l=C3=A4 >=20 > CHV has two display PHYs so there are also two cmnlane power wells. Add > the approriate code to power the wells up/down. >=20 > Like on VLV we do the cmnreset assert/deassert and the DPLL refclock > enabling at approriate times. >=20 > This code actually works on my bsw. >=20 > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 89 +++++++++++++++++++++++++++++++++++= ++++++ > 2 files changed, 90 insertions(+) >=20 > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index d246609..19e68d6 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -512,6 +512,7 @@ enum punit_power_well { > PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 =3D 9, > PUNIT_POWER_WELL_DPIO_RX0 =3D 10, > PUNIT_POWER_WELL_DPIO_RX1 =3D 11, > + PUNIT_POWER_WELL_DPIO_CMN_D =3D 12, > =20 > PUNIT_POWER_WELL_NUM, > }; > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index e2b956e..f88490b 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -6200,6 +6200,64 @@ static void vlv_dpio_cmn_power_well_disable(struct= drm_i915_private *dev_priv, > vlv_set_power_well(dev_priv, power_well, false); > } > =20 > +static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_= priv, > + struct i915_power_well *power_well) > +{ > + enum dpio_phy phy; > + > + WARN_ON_ONCE(power_well->data !=3D PUNIT_POWER_WELL_DPIO_CMN_BC && > + power_well->data !=3D PUNIT_POWER_WELL_DPIO_CMN_D); > + > + /* > + * Enable the CRI clock source so we can get at the > + * display and the reference clock for VGA > + * hotplug / manual detection. > + */ > + if (power_well->data =3D=3D PUNIT_POWER_WELL_DPIO_CMN_BC) { > + phy =3D DPIO_PHY0; > + I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | > + DPLL_REFA_CLK_ENABLE_VLV); > + I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | > + DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); Any reason the two clocks are enabled sequentially? For PHY1 you don't do this.. In any case: Reviewed-by: Imre Deak > + } else { > + phy =3D DPIO_PHY1; > + I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) | > + DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); > + } > + udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ > + vlv_set_power_well(dev_priv, power_well, true); > + > + /* Poll for phypwrgood signal */ > + if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1)) > + DRM_ERROR("Display PHY %d is not power up\n", phy); > + > + I915_WRITE(DISPLAY_PHY_CONTROL, > + PHY_COM_LANE_RESET_DEASSERT(phy, I915_READ(DISPLAY_PHY_CONTROL))); > +} > + > +static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev= _priv, > + struct i915_power_well *power_well) > +{ > + enum dpio_phy phy; > + > + WARN_ON_ONCE(power_well->data !=3D PUNIT_POWER_WELL_DPIO_CMN_BC && > + power_well->data !=3D PUNIT_POWER_WELL_DPIO_CMN_D); > + > + if (power_well->data =3D=3D PUNIT_POWER_WELL_DPIO_CMN_BC) { > + phy =3D DPIO_PHY0; > + assert_pll_disabled(dev_priv, PIPE_A); > + assert_pll_disabled(dev_priv, PIPE_B); > + } else { > + phy =3D DPIO_PHY1; > + assert_pll_disabled(dev_priv, PIPE_C); > + } > + > + I915_WRITE(DISPLAY_PHY_CONTROL, > + PHY_COM_LANE_RESET_ASSERT(phy, I915_READ(DISPLAY_PHY_CONTROL))); > + > + vlv_set_power_well(dev_priv, power_well, false); > +} > + > static void check_power_well_state(struct drm_i915_private *dev_priv, > struct i915_power_well *power_well) > { > @@ -6369,6 +6427,18 @@ EXPORT_SYMBOL_GPL(i915_release_power_well); > BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ > BIT(POWER_DOMAIN_INIT)) > =20 > +#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ > + BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ > + BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ > + BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ > + BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ > + BIT(POWER_DOMAIN_INIT)) > + > +#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ > + BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ > + BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ > + BIT(POWER_DOMAIN_INIT)) > + > static const struct i915_power_well_ops i9xx_always_on_power_well_ops = =3D { > .sync_hw =3D i9xx_always_on_power_well_noop, > .enable =3D i9xx_always_on_power_well_noop, > @@ -6498,6 +6568,13 @@ static struct i915_power_well vlv_power_wells[] = =3D { > }, > }; > =20 > +static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops =3D = { > + .sync_hw =3D vlv_power_well_sync_hw, > + .enable =3D chv_dpio_cmn_power_well_enable, > + .disable =3D chv_dpio_cmn_power_well_disable, > + .is_enabled =3D vlv_power_well_enabled, > +}; > + > static struct i915_power_well chv_power_wells[] =3D { > { > .name =3D "always-on", > @@ -6505,6 +6582,18 @@ static struct i915_power_well chv_power_wells[] = =3D { > .domains =3D VLV_ALWAYS_ON_POWER_DOMAINS, > .ops =3D &i9xx_always_on_power_well_ops, > }, > + { > + .name =3D "dpio-common-bc", > + .domains =3D CHV_DPIO_CMN_BC_POWER_DOMAINS, > + .data =3D PUNIT_POWER_WELL_DPIO_CMN_BC, > + .ops =3D &chv_dpio_cmn_power_well_ops, > + }, > + { > + .name =3D "dpio-common-d", > + .domains =3D CHV_DPIO_CMN_D_POWER_DOMAINS, > + .data =3D PUNIT_POWER_WELL_DPIO_CMN_D, > + .ops =3D &chv_dpio_cmn_power_well_ops, > + }, > }; > =20 > static struct i915_power_well *lookup_power_well(struct drm_i915_private= *dev_priv, --=-Uda4+EgN6oy3CuDaiUUv Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJT0kWUAAoJEORIIAnNuWDFK4MH/0k6+1kKOnD+Jld9Hn7zEwl3 awGzHVPDnK+C71Y0FTmjSA5pV3YOfUhDLPhLECeJ/9z4krvlMO2xnysieJ5ekjB9 T6URVDxd6+XJfSTiSjEN792NDwv0Q+C33NDefyG4NxcxlQfXUaieZbXvQIqQXEIQ 9mai4XidIFZb2T0iiW8eaJDnHecPhvnFwdcVoYQYsaktpH0uBgUreIRscqg+taVp YKOqmijijAELoNZ+ggVlAm3R5wRl0XaZFzt7tJKYPqnPaErhebkFm2nFHtKlMPmq egoL1g5/d294O5gBhJjhL2Sxfo+SUNAQAYYrqdD0ZCpXGZWYt8KXCQcKABEiXBU= =NnBW -----END PGP SIGNATURE----- --=-Uda4+EgN6oy3CuDaiUUv-- --===============0201356434== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0201356434==--