From: Imre Deak <imre.deak@intel.com>
To: ville.syrjala@linux.intel.com
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 18/40] drm/i915: Kill intel_reset_dpio()
Date: Fri, 25 Jul 2014 14:56:39 +0300 [thread overview]
Message-ID: <1406289399.23035.5.camel@intelbox> (raw)
In-Reply-To: <1403910271-24984-19-git-send-email-ville.syrjala@linux.intel.com>
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On Sat, 2014-06-28 at 02:04 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Both VLV and CHV handle the cmnreset stuff in the power well code now,
> so intel_reset_dpio() is no longer needed.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 31 -------------------------------
> 1 file changed, 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a16f635..3cd73f4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1511,34 +1511,6 @@ static void intel_init_dpio(struct drm_device *dev)
> }
> }
>
> -static void intel_reset_dpio(struct drm_device *dev)
> -{
> - struct drm_i915_private *dev_priv = dev->dev_private;
> -
> - if (IS_CHERRYVIEW(dev)) {
> - enum dpio_phy phy;
> - u32 val;
> -
> - for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
> - /* Poll for phypwrgood signal */
> - if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
> - PHY_POWERGOOD(phy), 1))
> - DRM_ERROR("Display PHY %d is not power up\n", phy);
> -
> - /*
> - * Deassert common lane reset for PHY.
> - *
> - * This should only be done on init and resume from S3
> - * with both PLLs disabled, or we risk losing DPIO and
> - * PLL synchronization.
> - */
> - val = I915_READ(DISPLAY_PHY_CONTROL);
> - I915_WRITE(DISPLAY_PHY_CONTROL,
> - PHY_COM_LANE_RESET_DEASSERT(phy, val));
> - }
> - }
> -}
> -
> static void vlv_enable_pll(struct intel_crtc *crtc)
> {
> struct drm_device *dev = crtc->base.dev;
> @@ -12473,8 +12445,6 @@ void intel_modeset_init_hw(struct drm_device *dev)
>
> intel_init_clock_gating(dev);
>
> - intel_reset_dpio(dev);
> -
> intel_enable_gt_powersave(dev);
> }
>
> @@ -12545,7 +12515,6 @@ void intel_modeset_init(struct drm_device *dev)
> }
>
> intel_init_dpio(dev);
> - intel_reset_dpio(dev);
>
> intel_cpu_pll_init(dev);
> intel_shared_dpll_init(dev);
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next prev parent reply other threads:[~2014-07-25 11:56 UTC|newest]
Thread overview: 109+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-27 23:03 [PATCH 00/40] CHV stuff mostly ville.syrjala
2014-06-27 23:03 ` [PATCH 01/40] drm/i915: Try to populate mem_freq for chv ville.syrjala
2014-07-12 13:27 ` Deepak S
2014-06-27 23:03 ` [PATCH 02/40] drm/i915: Use the cached min/min/rpe values in the vlv debugfs code ville.syrjala
2014-07-12 13:30 ` Deepak S
2014-07-11 14:04 ` Daniel Vetter
2014-06-27 23:03 ` [PATCH 03/40] drm/i915: Align chv rps min/max/rpe values ville.syrjala
2014-07-12 13:46 ` Deepak S
2014-07-28 15:17 ` Ville Syrjälä
2014-06-27 23:03 ` [PATCH 04/40] drm/i915: Populate mem_freq in init_gt_powerwave() ville.syrjala
2014-06-27 23:03 ` [PATCH 05/40] drm/i915: Don't disable PPGTT for CHV based in PCI rev ville.syrjala
2014-07-12 13:48 ` Deepak S
2014-07-11 13:59 ` Daniel Vetter
2014-06-27 23:03 ` [PATCH 06/40] drm/i915: Add cdclk change support for chv ville.syrjala
2014-07-29 16:51 ` Jesse Barnes
2014-07-29 17:59 ` Daniel Vetter
2014-07-29 18:07 ` Jesse Barnes
2014-07-29 18:39 ` Ville Syrjälä
2014-06-27 23:03 ` [PATCH 07/40] drm/i915: Disable cdclk changes for chv until Punit is ready ville.syrjala
2014-07-29 16:51 ` Jesse Barnes
2014-06-27 23:03 ` [PATCH 08/40] drm/i915: Leave DPLL ref clocks on ville.syrjala
2014-07-29 16:51 ` Jesse Barnes
2014-06-27 23:04 ` [PATCH 09/40] drm/i915: Split chv_update_pll() apart ville.syrjala
2014-07-29 16:53 ` Jesse Barnes
2014-06-27 23:04 ` [PATCH 10/40] drm/i915: Call encoder->post_disable() in intel_sanitize_encoder() ville.syrjala
2014-07-11 14:46 ` Barbalho, Rafael
2014-06-27 23:04 ` [PATCH 11/40] drm/i915: Call intel_{dp, hdmi}_prepare for chv ville.syrjala
2014-07-29 16:54 ` Jesse Barnes
2014-06-27 23:04 ` [PATCH 12/40] drm/i915: Clarify CHV swing margin/deemph bits ville.syrjala
2014-07-29 16:55 ` Jesse Barnes
2014-07-29 19:09 ` Daniel Vetter
2014-06-27 23:04 ` [PATCH 13/40] drm/i915: Make sure hardware uses the correct swing margin/deemph bits on chv ville.syrjala
2014-06-27 23:04 ` [PATCH 14/40] drm/i915: Override display PHY TX FIFO reset master " ville.syrjala
2014-07-29 16:57 ` Jesse Barnes
2014-08-01 13:10 ` Ville Syrjälä
2014-06-27 23:04 ` [PATCH 15/40] drm/i915: Clear TX FIFO reset master override bits " ville.syrjala
2014-08-01 13:23 ` [PATCH v2 " ville.syrjala
2014-06-27 23:04 ` [PATCH 16/40] drm/i915: Add chv_power_wells[] ville.syrjala
2014-07-11 14:09 ` Barbalho, Rafael
2014-07-30 11:18 ` Daniel Vetter
2014-06-27 23:04 ` [PATCH 17/40] drm/i915: Add chv cmnlane power wells ville.syrjala
2014-07-25 11:55 ` Imre Deak
2014-07-28 15:18 ` Ville Syrjälä
2014-06-27 23:04 ` [PATCH 18/40] drm/i915: Kill intel_reset_dpio() ville.syrjala
2014-07-25 11:56 ` Imre Deak [this message]
2014-06-27 23:04 ` [PATCH 19/40] drm/i915: Add disp2d power well for chv ville.syrjala
2014-07-25 13:23 ` Imre Deak
2014-06-27 23:04 ` [PATCH 20/40] drm/i915: Add per-pipe power wells " ville.syrjala
2014-07-25 13:24 ` Imre Deak
2014-06-27 23:04 ` [PATCH 21/40] drm/i915: Add chv port B and C TX wells ville.syrjala
2014-07-25 13:25 ` Imre Deak
2014-06-27 23:04 ` [PATCH 22/40] drm/i915: Add chv port D " ville.syrjala
2014-07-25 13:30 ` Imre Deak
2014-07-28 9:11 ` Daniel Vetter
2014-07-28 15:19 ` Ville Syrjälä
2014-07-29 9:54 ` Imre Deak
2014-07-29 10:27 ` Daniel Vetter
2014-06-27 23:04 ` [PATCH 23/40] drm/i915: Fix drain latency precision multipler for VLV ville.syrjala
2014-07-31 15:08 ` Paulo Zanoni
2014-07-31 15:16 ` Ville Syrjälä
2014-07-31 17:05 ` Paulo Zanoni
2014-07-31 17:13 ` Ville Syrjälä
2014-07-31 18:06 ` Paulo Zanoni
2014-06-27 23:04 ` [PATCH 24/40] drm/i915: Fix threshold for choosing 32 vs. 64 precisions for VLV DDL values ville.syrjala
2014-07-31 18:08 ` Paulo Zanoni
2014-08-01 12:33 ` Ville Syrjälä
2014-06-27 23:04 ` [PATCH 25/40] drm/i915: Fill out the FWx watermark register defines ville.syrjala
2014-07-31 20:16 ` Paulo Zanoni
2014-08-01 11:26 ` Ville Syrjälä
2014-08-01 12:28 ` [PATCH v2 " ville.syrjala
2014-06-27 23:04 ` [PATCH 26/40] drm/i915: Parametrize VLV_DDL registers ville.syrjala
2014-07-30 20:43 ` Paulo Zanoni
2014-07-31 12:05 ` Ville Syrjälä
2014-07-31 12:11 ` [PATCH v2 " ville.syrjala
2014-06-27 23:04 ` [PATCH 27/40] drm/i915: Split a few long debug prints ville.syrjala
2014-07-29 16:59 ` Jesse Barnes
2014-06-27 23:04 ` [PATCH 28/40] drm/i915: Add cherryview_update_wm() ville.syrjala
2014-07-31 20:57 ` Paulo Zanoni
2014-08-01 11:33 ` Ville Syrjälä
2014-08-01 12:36 ` [PATCH v2 " ville.syrjala
2014-08-01 14:29 ` Paulo Zanoni
2014-06-27 23:04 ` [PATCH 29/40] drm/i915: Refactor Broadwell PIPE_CONTROL emission into a helper ville.syrjala
2014-07-29 16:59 ` Jesse Barnes
2014-07-29 18:01 ` Daniel Vetter
2014-07-30 20:23 ` Daniel Vetter
2014-06-27 23:04 ` [PATCH 30/40] drm/i915: Add the WaCsStallBeforeStateCacheInvalidate:bdw workaround ville.syrjala
2014-07-11 13:30 ` Barbalho, Rafael
2014-06-27 23:04 ` [PATCH 31/40] drm/i916: Init chv workarounds at render ring init ville.syrjala
2014-07-30 12:35 ` Barbalho, Rafael
2014-07-30 12:48 ` Ville Syrjälä
2014-06-27 23:04 ` [PATCH 32/40] drm/i915: Hack to tie both common lanes together on chv ville.syrjala
2014-07-30 12:12 ` Barbalho, Rafael
2014-06-27 23:04 ` [PATCH 33/40] drm/i915: Polish the chv cmnlane resrt macros ville.syrjala
2014-07-30 12:13 ` Barbalho, Rafael
2014-06-27 23:04 ` [PATCH 34/40] drm/i915: Add DP training pattern 3 for CHV ville.syrjala
2014-07-29 17:01 ` Jesse Barnes
2014-07-29 18:04 ` Daniel Vetter
2014-07-29 18:34 ` Ville Syrjälä
2014-07-29 19:12 ` Daniel Vetter
2014-06-27 23:04 ` [PATCH 35/40] drm/i915: Fix vdd locking ville.syrjala
2014-06-27 23:04 ` [PATCH 36/40] drm/i915: Allow vdd_off when vdd is already off ville.syrjala
2014-06-27 23:04 ` [PATCH 37/40] drm/i915: Fix eDP link training when switching pipes ville.syrjala
2014-06-30 21:52 ` Jesse Barnes
2014-07-29 18:06 ` Daniel Vetter
2014-07-29 19:18 ` Ville Syrjälä
2014-07-29 19:23 ` Daniel Vetter
2014-06-27 23:04 ` [PATCH 38/40] drm/i915: Track which port is using which pipe's power sequencer ville.syrjala
2014-06-27 23:04 ` [PATCH 39/40] drm/i915: Kick the power sequencer before AUX transactions ville.syrjala
2014-06-27 23:04 ` [PATCH 40/40] drm/i915: Unstuck power sequencer when lighting up a DP port ville.syrjala
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