From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 20/40] drm/i915: Add per-pipe power wells for chv Date: Fri, 25 Jul 2014 16:24:43 +0300 Message-ID: <1406294683.23035.7.camel@intelbox> References: <1403910271-24984-1-git-send-email-ville.syrjala@linux.intel.com> <1403910271-24984-21-git-send-email-ville.syrjala@linux.intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0650276126==" Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 438796E823 for ; Fri, 25 Jul 2014 06:24:48 -0700 (PDT) In-Reply-To: <1403910271-24984-21-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0650276126== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-zxrPVjkGV1eaajdCYmB+" --=-zxrPVjkGV1eaajdCYmB+ Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Sat, 2014-06-28 at 02:04 +0300, ville.syrjala@linux.intel.com wrote: > From: Ville Syrj=C3=A4l=C3=A4 >=20 > CHV has a power well for each pipe. Add the code to deal with them. >=20 > The Punit in current hardware doesn't seem ready for this yet, so > leave it iffed out. >=20 > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 Reviewed-by: Imre Deak > --- > drivers/gpu/drm/i915/i915_reg.h | 12 ++++ > drivers/gpu/drm/i915/intel_pm.c | 126 ++++++++++++++++++++++++++++++++++= ++++++ > 2 files changed, 138 insertions(+) >=20 > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index 19e68d6..3d1fef4 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -499,6 +499,18 @@ > #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) > #define DSPFREQGUAR_SHIFT 14 > #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) > +#define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) > +#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) > +#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) > +#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) > +#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) > +#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe)) > +#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16)) > +#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe)) > +#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe)) > +#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe)) > +#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe)) > +#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe)) > =20 > /* See the PUNIT HAS v0.8 for the below bits */ > enum punit_power_well { > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 46394fc..de5416b 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -6258,6 +6258,95 @@ static void chv_dpio_cmn_power_well_disable(struct= drm_i915_private *dev_priv, > vlv_set_power_well(dev_priv, power_well, false); > } > =20 > +static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_pri= v, > + struct i915_power_well *power_well) > +{ > + enum pipe pipe =3D power_well->data; > + bool enabled; > + u32 state, ctrl; > + > + mutex_lock(&dev_priv->rps.hw_lock); > + > + state =3D vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pip= e); > + /* > + * We only ever set the power-on and power-gate states, anything > + * else is unexpected. > + */ > + WARN_ON(state !=3D DP_SSS_PWR_ON(pipe) && state !=3D DP_SSS_PWR_GATE(pi= pe)); > + enabled =3D state =3D=3D DP_SSS_PWR_ON(pipe); > + > + /* > + * A transient state at this point would mean some unexpected party > + * is poking at the power controls too. > + */ > + ctrl =3D vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe= ); > + WARN_ON(ctrl << 16 !=3D state); > + > + mutex_unlock(&dev_priv->rps.hw_lock); > + > + return enabled; > +} > + > +static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, > + struct i915_power_well *power_well, > + bool enable) > +{ > + enum pipe pipe =3D power_well->data; > + u32 state; > + u32 ctrl; > + > + state =3D enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); > + > + mutex_lock(&dev_priv->rps.hw_lock); > + > +#define COND \ > + ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) =3D= =3D state) > + > + if (COND) > + goto out; > + > + ctrl =3D vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); > + ctrl &=3D ~DP_SSC_MASK(pipe); > + ctrl |=3D enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); > + vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); > + > + if (wait_for(COND, 100)) > + DRM_ERROR("timout setting power well state %08x (%08x)\n", > + state, > + vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); > + > +#undef COND > + > +out: > + mutex_unlock(&dev_priv->rps.hw_lock); > +} > + > +static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_pri= v, > + struct i915_power_well *power_well) > +{ > + chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0); > +} > + > +static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv= , > + struct i915_power_well *power_well) > +{ > + WARN_ON_ONCE(power_well->data !=3D PIPE_A && > + power_well->data !=3D PIPE_B && > + power_well->data !=3D PIPE_C); > + > + chv_set_pipe_power_well(dev_priv, power_well, true); > +} > + > +static void chv_pipe_power_well_disable(struct drm_i915_private *dev_pri= v, > + struct i915_power_well *power_well) > +{ > + WARN_ON_ONCE(power_well->data !=3D PIPE_A && > + power_well->data !=3D PIPE_B && > + power_well->data !=3D PIPE_C); > + > + chv_set_pipe_power_well(dev_priv, power_well, false); > +} > + > static void check_power_well_state(struct drm_i915_private *dev_priv, > struct i915_power_well *power_well) > { > @@ -6427,6 +6516,18 @@ EXPORT_SYMBOL_GPL(i915_release_power_well); > BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ > BIT(POWER_DOMAIN_INIT)) > =20 > +#define CHV_PIPE_A_POWER_DOMAINS ( \ > + BIT(POWER_DOMAIN_PIPE_A) | \ > + BIT(POWER_DOMAIN_INIT)) > + > +#define CHV_PIPE_B_POWER_DOMAINS ( \ > + BIT(POWER_DOMAIN_PIPE_B) | \ > + BIT(POWER_DOMAIN_INIT)) > + > +#define CHV_PIPE_C_POWER_DOMAINS ( \ > + BIT(POWER_DOMAIN_PIPE_C) | \ > + BIT(POWER_DOMAIN_INIT)) > + > #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ > BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ > BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ > @@ -6568,6 +6669,13 @@ static struct i915_power_well vlv_power_wells[] = =3D { > }, > }; > =20 > +static const struct i915_power_well_ops chv_pipe_power_well_ops =3D { > + .sync_hw =3D chv_pipe_power_well_sync_hw, > + .enable =3D chv_pipe_power_well_enable, > + .disable =3D chv_pipe_power_well_disable, > + .is_enabled =3D chv_pipe_power_well_enabled, > +}; > + > static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops =3D = { > .sync_hw =3D vlv_power_well_sync_hw, > .enable =3D chv_dpio_cmn_power_well_enable, > @@ -6589,6 +6697,24 @@ static struct i915_power_well chv_power_wells[] = =3D { > .data =3D PUNIT_POWER_WELL_DISP2D, > .ops =3D &vlv_display_power_well_ops, > }, > + { > + .name =3D "pipe-a", > + .domains =3D CHV_PIPE_A_POWER_DOMAINS, > + .data =3D PIPE_A, > + .ops =3D &chv_pipe_power_well_ops, > + }, > + { > + .name =3D "pipe-b", > + .domains =3D CHV_PIPE_B_POWER_DOMAINS, > + .data =3D PIPE_B, > + .ops =3D &chv_pipe_power_well_ops, > + }, > + { > + .name =3D "pipe-c", > + .domains =3D CHV_PIPE_C_POWER_DOMAINS, > + .data =3D PIPE_C, > + .ops =3D &chv_pipe_power_well_ops, > + }, > #endif > { > .name =3D "dpio-common-bc", --=-zxrPVjkGV1eaajdCYmB+ Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJT0lqbAAoJEORIIAnNuWDFbDUIAKCghN2EntGJ3RjisY3lsEA+ YIwK408Y9rmE/sIR0M4zJBJozDIvd6Xx4YnnRScwZ8YPvzzKRldJb6AGu3IgJh66 TFAWCokBCibCUVlcID3pfE6s1TASLBX+ogoIuBupeTLPw4SGHq9yylaMBf02HXXm zf73zgwSpH2ZLNldBH/JWXLSTJm8Jk1Flj8860dR1KEAKe8aCyIjupT4esy+dIb0 3iYs21E61coqPlcc+6XX9NzqLRzj1AOk85kHk+feUAMCZrbd4SaYgq/Ug+SqQet1 22pDotCKWuNWbKQlLZecmxOiNK5asDYivORPsiuIpy+fmYPnXtImlBiiAj9Plec= =C/HI -----END PGP SIGNATURE----- --=-zxrPVjkGV1eaajdCYmB+-- --===============0650276126== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0650276126==--