Re: [PATCH 24/40] drm/i915: Fix threshold for choosing 32 vs. 64 precisions for VLV DDL values

Ville Syrjälä
2014-08-01T12:33:29Z

On Thu, Jul 31, 2014 at 03:08:29PM -0300, Paulo Zanoni wrote:
> 2014-06-27 20:04 GMT-03:00 <ville.syrjala@linux.intel.com>:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > The DDL registers can hold 7bit numbers. Make the most of those seven
> > bits by adjusting the threshold where we switch between the 64 vs. 32
> > precision multipliers.
> >
> > Also we compute 'entries' to make the decision about precision, and then
> > we recompute the same value to calculate the actual drain latency. Just
> > use the already calculate 'entries' there.
>
> Just an addition: don't we also want to WARN in case "entires < 64"
> (or in case the final result exceeds 7 bits, which is equivalent)?
> Could be a separate patch too.

Yeah we could WARN when things go south. But there are some patches from
Gajanan pending that touch this code too, so probably best to wait until
those have gone in to avoid too much rebase pain.

>
> With or without that: Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 9 ++++-----
> > 1 file changed, 4 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 9413184..3aa7959 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -1252,15 +1252,14 @@ static bool vlv_compute_drain_latency(struct drm_device *dev,
> > pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
> >
> > entries = (clock / 1000) * pixel_size;
> > - *plane_prec_mult = (entries > 256) ?
> > + *plane_prec_mult = (entries > 128) ?
> > DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
> > - *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
> > - pixel_size);
> > + *plane_dl = (64 * (*plane_prec_mult) * 4) / entries;
> >
> > entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
> > - *cursor_prec_mult = (entries > 256) ?
> > + *cursor_prec_mult = (entries > 128) ?
> > DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
> > - *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
> > + *cursor_dl = (64 * (*cursor_prec_mult) * 4) / entries;
> >
> > return true;
> > }
> > --
> > 1.8.5.5
> >
> > _______________________________________________
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> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Paulo Zanoni

--
Ville Syrjälä
Intel OTC