[PATCH 15/40] drm/i915: Clear TX FIFO reset master override bits on chv

ville.syrjala
2014-06-27T23:07:28Z

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Clear the override bits to make sure the hardware maanages
the TX FIFO reset master on its own.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 20 +++-----------------
drivers/gpu/drm/i915/intel_hdmi.c | 20 +++-----------------
2 files changed, 6 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 814a950..739dc43 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2139,27 +2139,13 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)

mutex_lock(&dev_priv->dpio_lock);

- /* TX FIFO reset source */
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
- val |= DPIO_LEFT_TXFIFO_RST_MASTER2;
- val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
-
+ /* allow hardware to manage TX FIFO reset source */
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
- val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
- val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER;
- val |= DPIO_LANEDESKEW_STRAP_OVRD;
+ val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);

- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
- val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
- val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER2;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
-
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
- val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
- val |= DPIO_RIGHT_TXFIFO_RST_MASTER;
- val |= DPIO_LANEDESKEW_STRAP_OVRD;
+ val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);

/* Deassert soft data lane reset*/
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 47430d5..98bdf02 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1358,27 +1358,13 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)

mutex_lock(&dev_priv->dpio_lock);

- /* TX FIFO reset source */
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
- val |= DPIO_LEFT_TXFIFO_RST_MASTER2;
- val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
-
+ /* allow hardware to manage TX FIFO reset source */
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
- val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
- val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER;
- val |= DPIO_LANEDESKEW_STRAP_OVRD;
+ val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);

- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
- val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
- val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER2;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
-
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
- val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
- val |= DPIO_RIGHT_TXFIFO_RST_MASTER;
- val |= DPIO_LANEDESKEW_STRAP_OVRD;
+ val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);

/* Deassert soft data lane reset*/
--
1.8.5.5