Re: [PATCH 33/40] drm/i915: Polish the chv cmnlane resrt macros

Barbalho, Rafael
2014-07-30T12:13:37Z

> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
> Of ville.syrjala@linux.intel.com
> Sent: Saturday, June 28, 2014 12:04 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 33/40] drm/i915: Polish the chv cmnlane resrt
> macros
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Replace the semi-funky cmnlane assert/deassert macros with something a
> bit more conventional. Also protect the macro arguments properly (also
> for PHY_POWERGOOD()).
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 7 ++-----
> drivers/gpu/drm/i915/intel_pm.c | 8 ++++----
> 2 files changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 60dd19c..85b59c4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1717,12 +1717,9 @@ enum punit_power_well {
> #define DPIO_PHY_STATUS (VLV_DISPLAY_BASE +
> 0x6240)
> #define DPLL_PORTD_READY_MASK (0xf)
> #define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)
> -#define PHY_COM_LANE_RESET_DEASSERT(phy, val) \
> - ((phy == DPIO_PHY0) ? (val | 1) : (val | 2))
> -#define PHY_COM_LANE_RESET_ASSERT(phy, val) \
> - ((phy == DPIO_PHY0) ? (val & ~1) : (val & ~2))
> +#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
> #define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)
> -#define PHY_POWERGOOD(phy) ((phy == DPIO_PHY0) ? (1<<31) :
> (1<<30))
> +#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) :
> (1<<30))
>
> /*
> * The i830 generation, in LVDS mode, defines P1 as the bit number set
> within
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 879d14c..f193d95 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6280,8 +6280,8 @@ static void
> chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
> if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
> PHY_POWERGOOD(phy), 1))
> DRM_ERROR("Display PHY %d is not power up\n", phy);
>
> - I915_WRITE(DISPLAY_PHY_CONTROL,
> - PHY_COM_LANE_RESET_DEASSERT(phy,
> I915_READ(DISPLAY_PHY_CONTROL)));
> + I915_WRITE(DISPLAY_PHY_CONTROL,
> I915_READ(DISPLAY_PHY_CONTROL) |
> + PHY_COM_LANE_RESET_DEASSERT(phy));
> }
>
> static void chv_dpio_cmn_power_well_disable(struct drm_i915_private
> *dev_priv,
> @@ -6301,8 +6301,8 @@ static void
> chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
> assert_pll_disabled(dev_priv, PIPE_C);
> }
>
> - I915_WRITE(DISPLAY_PHY_CONTROL,
> - PHY_COM_LANE_RESET_ASSERT(phy,
> I915_READ(DISPLAY_PHY_CONTROL)));
> + I915_WRITE(DISPLAY_PHY_CONTROL,
> I915_READ(DISPLAY_PHY_CONTROL) &
> + ~PHY_COM_LANE_RESET_DEASSERT(phy));
>
> vlv_set_power_well(dev_priv, power_well, false);
> }
> --
> 1.8.5.5

Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>

>
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