[PATCH 00/40] CHV stuff mostly

ville.syrjala
2014-06-27T23:04:36Z

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

I was slaving over my bsw for most of the past week and this is the
result. It should really be split up into several series, but no
time now when vacation is calling. So I figured that I'll just post
the entire pile and disappear.

The whole lot can be found here (sitting on top of my earlier vlv
cdclk patches):
git://gitorious.org/vsyrjala/linux.git chv_stuff_5

This is mostly display stuff, with a few workaround things to make the
GT happy. The display stuff is mostly about power wells (several as of
now non working patches are also included) and the thrice cursed panel
power sequencer. Also some watermark patches are included.

The power sequencer stuff should apply equally to VLV, but I don't
have a suitable machine nor time to try it. I think it would fix a
lot of the weird link training failures people may have seen on VLV.
If someone else wants to play with it I recommend a machine with eDP+DP
and doing stuff like:
xrandr --output DP1 --off --output eDP1 --off
xrandr --output DP1 --mode 1920x1080 --crtc 1 --output eDP1 --mode 1920x1080 --crtc 0
xrandr --output DP1 --off --output eDP1 --off
xrandr --output DP1 --mode 1920x1080 --crtc 0 --output eDP1 --mode 1920x1080 --crtc 1
xrandr --output DP1 --off --output eDP1 --off
xrandr --output DP1 --mode 1920x1080 --crtc 1 --output eDP1 --mode 1920x1080 --crtc 0
...
or even just
xrandr --output eDP1 --off
xrandr --output eDP1 --mode 1920x1080 --crtc 0
xrandr --output eDP1 --off
xrandr --output eDP1 --mode 1920x1080 --crtc 1
xrandr --output eDP1 --off
xrandr --output eDP1 --mode 1920x1080 --crtc 0
...
so switching the pipe->port mapping around a lot.

The power well refcounts vs. the edp vdd code is still a mess. Occasionally it overflows
the refcounts, and occasionally it underflows. So it there are display problems I would
suggest looking at /sys/kernel/debug/dri/0/i915_power_domain_info and chencking if something
is 0 (or even negative) when it shouldn't be.

Kenneth Graunke (2):
drm/i915: Refactor Broadwell PIPE_CONTROL emission into a helper.
drm/i915: Add the WaCsStallBeforeStateCacheInvalidate:bdw workaround.

Ville Syrjälä (37):
drm/i915: Try to populate mem_freq for chv
drm/i915: Use the cached min/min/rpe values in the vlv debugfs code
drm/i915: Align chv rps min/max/rpe values
drm/i915: Populate mem_freq in init_gt_powerwave()
drm/i915: Don't disable PPGTT for CHV based in PCI rev
drm/i915: Add cdclk change support for chv
drm/i915: Disable cdclk changes for chv until Punit is ready
drm/i915: Leave DPLL ref clocks on
drm/i915: Split chv_update_pll() apart
drm/i915: Call encoder->post_disable() in intel_sanitize_encoder()
drm/i915: Call intel_{dp,hdmi}_prepare for chv
drm/i915: Clarify CHV swing margin/deemph bits
drm/i915: Make sure hardware uses the correct swing margin/deemph bits
on chv
drm/i915: Override display PHY TX FIFO reset master on chv
drm/i915: Clear TX FIFO reset master override bits on chv
drm/i915: Add chv_power_wells[]
drm/i915: Add chv cmnlane power wells
drm/i915: Kill intel_reset_dpio()
drm/i915: Add disp2d power well for chv
drm/i915: Add per-pipe power wells for chv
drm/i915: Add chv port B and C TX wells
drm/i915: Add chv port D TX wells
drm/i915: Fix threshold for choosing 32 vs. 64 precisions for VLV DDL
values
drm/i915: Fill out the FWx watermark register defines
drm/i915: Parametrize VLV_DDL registers
drm/i915: Split a few long debug prints
drm/i915: Add cherryview_update_wm()
drm/i916: Init chv workarounds at render ring init
drm/i915: Hack to tie both common lanes together on chv
drm/i915: Polish the chv cmnlane resrt macros
drm/i915: Add DP training pattern 3 for CHV
drm/i915: Fix vdd locking
drm/i915: Allow vdd_off when vdd is already off
drm/i915: Fix eDP link training when switching pipes
drm/i915: Track which port is using which pipe's power sequencer
drm/i915: Kick the power sequencer before AUX transactions
drm/i915: Unstuck power sequencer when lighting up a DP port

Zhenyu Wang (1):
drm/i915: Fix drain latency precision multipler for VLV

drivers/gpu/drm/i915/i915_debugfs.c | 27 +-
drivers/gpu/drm/i915/i915_drv.h | 2 -
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 263 +++++++++++----
drivers/gpu/drm/i915/intel_display.c | 123 ++++---
drivers/gpu/drm/i915/intel_dp.c | 469 +++++++++++++++++++++++---
drivers/gpu/drm/i915/intel_drv.h | 6 +
drivers/gpu/drm/i915/intel_hdmi.c | 29 +-
drivers/gpu/drm/i915/intel_pm.c | 565 ++++++++++++++++++++++++++------
drivers/gpu/drm/i915/intel_ringbuffer.c | 84 ++++-
10 files changed, 1296 insertions(+), 275 deletions(-)

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1.8.5.5