Re: [PATCH 30/40] drm/i915: Add the WaCsStallBeforeStateCacheInvalidate:bdw workaround.

Barbalho, Rafael
2014-07-11T13:30:56Z

> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
> Of ville.syrjala@linux.intel.com
> Sent: Saturday, June 28, 2014 12:04 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 30/40] drm/i915: Add the
> WaCsStallBeforeStateCacheInvalidate:bdw workaround.
>
> From: Kenneth Graunke <kenneth@whitecape.org>
>
> On Broadwell, any PIPE_CONTROL with the "State Cache Invalidate" bit set
> must be preceded by a PIPE_CONTROL with the "CS Stall" bit set.
>
> Documented on the BSpec 3D workarounds page.
>
> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
> [vsyrjala: add chv w/a note too]
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

There is a gotcha here that this workaround name has been used for a different bug in Gen7.5 and below. The workaround name clash came from the docs rather than a mistake by the patch authors, this is the correct workaround for all gen8 based devices

Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>

> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 97796b1..ceb1295 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -424,6 +424,14 @@ gen8_render_ring_flush(struct intel_engine_cs
> *ring,
> flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
> flags |= PIPE_CONTROL_QW_WRITE;
> flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
> +
> + /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
> + ret = gen8_emit_pipe_control(ring,
> + PIPE_CONTROL_CS_STALL |
> +
> PIPE_CONTROL_STALL_AT_SCOREBOARD,
> + 0);
> + if (ret)
> + return ret;
> }
>
> return gen8_emit_pipe_control(ring, flags, scratch_addr);
> --
> 1.8.5.5
>
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