Re: [PATCH 22/40] drm/i915: Add chv port D TX wells

[Imre Deak <imre.deak@intel.com>]

[-- Attachment #1.1: Type: text/plain, Size: 2895 bytes --]

On Sat, 2014-06-28 at 02:04 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add the TX wells for port D. The Punit subsystem numbers are a total
> guess at this time. Also I'm not sure these even exist. Certainly the
> Punit in current hardware doesn't deal with these.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |  4 ++++
>  drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++++++++++++++
>  2 files changed, 27 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3d1fef4..191df9e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -525,6 +525,10 @@ enum punit_power_well {
>  	PUNIT_POWER_WELL_DPIO_RX0		= 10,
>  	PUNIT_POWER_WELL_DPIO_RX1		= 11,
>  	PUNIT_POWER_WELL_DPIO_CMN_D		= 12,
> +	/* FIXME: guesswork below */
> +	PUNIT_POWER_WELL_DPIO_TX_D_LANES_01	= 13,
> +	PUNIT_POWER_WELL_DPIO_TX_D_LANES_23	= 14,
> +	PUNIT_POWER_WELL_DPIO_RX2		= 15,
>  
>  	PUNIT_POWER_WELL_NUM,
>  };
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index cae936c..55f3e6b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6540,6 +6540,15 @@ EXPORT_SYMBOL_GPL(i915_release_power_well);
>  	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\
>  	BIT(POWER_DOMAIN_INIT))
>  
> +#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS (	\
> +	BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |	\
> +	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\
> +	BIT(POWER_DOMAIN_INIT))
> +
> +#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS (	\
> +	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\

Atm, for all other ports we power up all lanes regardless of the actual
configuration (until the PHY side setup is proved to work fine). So for
consistency I'd do the same here too. With that change:

Reviewed-by: Imre Deak <imre.deak@intel.com>

> +	BIT(POWER_DOMAIN_INIT))
> +
>  static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
>  	.sync_hw = i9xx_always_on_power_well_noop,
>  	.enable = i9xx_always_on_power_well_noop,
> @@ -6757,6 +6766,20 @@ static struct i915_power_well chv_power_wells[] = {
>  		.ops = &vlv_dpio_power_well_ops,
>  		.data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
>  	},
> +	{
> +		.name = "dpio-tx-d-01",
> +		.domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
> +			   CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
> +		.ops = &vlv_dpio_power_well_ops,
> +		.data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
> +	},
> +	{
> +		.name = "dpio-tx-d-23",
> +		.domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
> +			   CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
> +		.ops = &vlv_dpio_power_well_ops,
> +		.data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
> +	},
>  #endif
>  };
>  


[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 490 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx