From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: [PATCH 2/3] drm/i915: get runtime PM when pinning sprite objects Date: Mon, 28 Jul 2014 15:37:14 -0300 Message-ID: <1406572636-1809-4-git-send-email-przanoni@gmail.com> References: <1406572636-1809-1-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-vc0-f171.google.com (mail-vc0-f171.google.com [209.85.220.171]) by gabe.freedesktop.org (Postfix) with ESMTP id EEA516E3F1 for ; Mon, 28 Jul 2014 11:37:42 -0700 (PDT) Received: by mail-vc0-f171.google.com with SMTP id hq11so11984355vcb.2 for ; Mon, 28 Jul 2014 11:37:42 -0700 (PDT) In-Reply-To: <1406572636-1809-1-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni , stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org From: Paulo Zanoni Otherwise we may get WARNs saying we're writing registers while runtime suspended. Testcase: igt/pm_rpm/legacy-planes Testcase: igt/pm_rpm/legacy-planes-dpms Cc: stable@vger.kernel.org Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_sprite.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index d34a569..8c5a8f7 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -821,6 +821,7 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, uint32_t src_w, uint32_t src_h) { struct drm_device *dev = plane->dev; + struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_plane *intel_plane = to_intel_plane(plane); enum pipe pipe = intel_crtc->pipe; @@ -1009,7 +1010,9 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, * primary plane requires 256KiB alignment with 64 PTE padding, * the sprite planes only require 128KiB alignment and 32 PTE padding. */ + intel_runtime_pm_get(dev_priv); ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); + intel_runtime_pm_put(dev_priv); i915_gem_track_fb(old_obj, obj, INTEL_FRONTBUFFER_SPRITE(pipe)); -- 2.0.1