From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 22/40] drm/i915: Add chv port D TX wells Date: Tue, 29 Jul 2014 12:54:36 +0300 Message-ID: <1406627676.9702.15.camel@intelbox> References: <1403910271-24984-1-git-send-email-ville.syrjala@linux.intel.com> <1403910271-24984-23-git-send-email-ville.syrjala@linux.intel.com> <1406295029.23035.12.camel@intelbox> <20140728151919.GK27580@intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1915172290==" Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 5BD046E38B for ; Tue, 29 Jul 2014 02:55:48 -0700 (PDT) In-Reply-To: <20140728151919.GK27580@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Ville =?ISO-8859-1?Q?Syrj=E4l=E4?= Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============1915172290== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-wiZAOdaOZ9k1PKst0+gK" --=-wiZAOdaOZ9k1PKst0+gK Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, 2014-07-28 at 18:19 +0300, Ville Syrj=C3=A4l=C3=A4 wrote: > On Fri, Jul 25, 2014 at 04:30:29PM +0300, Imre Deak wrote: > > On Sat, 2014-06-28 at 02:04 +0300, ville.syrjala@linux.intel.com wrote: > > > From: Ville Syrj=C3=A4l=C3=A4 > > >=20 > > > Add the TX wells for port D. The Punit subsystem numbers are a total > > > guess at this time. Also I'm not sure these even exist. Certainly the > > > Punit in current hardware doesn't deal with these. > > >=20 > > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 > > > --- > > > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > > > drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++++++++++++++ > > > 2 files changed, 27 insertions(+) > > >=20 > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i= 915_reg.h > > > index 3d1fef4..191df9e 100644 > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > @@ -525,6 +525,10 @@ enum punit_power_well { > > > PUNIT_POWER_WELL_DPIO_RX0 =3D 10, > > > PUNIT_POWER_WELL_DPIO_RX1 =3D 11, > > > PUNIT_POWER_WELL_DPIO_CMN_D =3D 12, > > > + /* FIXME: guesswork below */ > > > + PUNIT_POWER_WELL_DPIO_TX_D_LANES_01 =3D 13, > > > + PUNIT_POWER_WELL_DPIO_TX_D_LANES_23 =3D 14, > > > + PUNIT_POWER_WELL_DPIO_RX2 =3D 15, > > > =20 > > > PUNIT_POWER_WELL_NUM, > > > }; > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/i= ntel_pm.c > > > index cae936c..55f3e6b 100644 > > > --- a/drivers/gpu/drm/i915/intel_pm.c > > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > > @@ -6540,6 +6540,15 @@ EXPORT_SYMBOL_GPL(i915_release_power_well); > > > BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ > > > BIT(POWER_DOMAIN_INIT)) > > > =20 > > > +#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \ > > > + BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ > > > + BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ > > > + BIT(POWER_DOMAIN_INIT)) > > > + > > > +#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \ > > > + BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ > >=20 > > Atm, for all other ports we power up all lanes regardless of the actual > > configuration (until the PHY side setup is proved to work fine). So for > > consistency I'd do the same here too. With that change: >=20 > We do that here too. '.domains =3D 01 | 23' for both tx-d wells. Or am I > missing something? Ah, right I should've read a couple of lines below. So my above comment can be ignored and my r-b applies as-is. > > Reviewed-by: Imre Deak > >=20 > > > + BIT(POWER_DOMAIN_INIT)) > > > + > > > static const struct i915_power_well_ops i9xx_always_on_power_well_op= s =3D { > > > .sync_hw =3D i9xx_always_on_power_well_noop, > > > .enable =3D i9xx_always_on_power_well_noop, > > > @@ -6757,6 +6766,20 @@ static struct i915_power_well chv_power_wells[= ] =3D { > > > .ops =3D &vlv_dpio_power_well_ops, > > > .data =3D PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, > > > }, > > > + { > > > + .name =3D "dpio-tx-d-01", > > > + .domains =3D CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | > > > + CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, > > > + .ops =3D &vlv_dpio_power_well_ops, > > > + .data =3D PUNIT_POWER_WELL_DPIO_TX_D_LANES_01, > > > + }, > > > + { > > > + .name =3D "dpio-tx-d-23", > > > + .domains =3D CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | > > > + CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, > > > + .ops =3D &vlv_dpio_power_well_ops, > > > + .data =3D PUNIT_POWER_WELL_DPIO_TX_D_LANES_23, > > > + }, > > > #endif > > > }; > > > =20 > >=20 >=20 >=20 >=20 --=-wiZAOdaOZ9k1PKst0+gK Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJT129cAAoJEORIIAnNuWDFYp8H/0a975G15mbhbgGOOqbZ6JJI 3tNr8umN+NwTFmDU4dKh2SfFCgEOMvRgRc/SwLVZMNxgtS7LZTa2Es7iKA3jN8Vy LF/0qlrkE77F3Ctn4988vBfsCUH0f+RyRHy+/LlQV/7+vzg0U18mFf2hTygeGWq9 gJDI6YerisZBY3otohuF/dSlFcYKtyqNvE2yLK4/YaxEgCSzwjI3zl+wv27fW/tV W6uuingkylaWWtRoYshwhEzmw1PndHK5yS5sBhsLuEyvWfb0pR+aE4QvCkRw89P+ a4NOpDOmqi7ELK5SkqvdxVMRtvsg12o3k3ji6MISRFwsu/tppHDhkD3cLI7/+JQ= =cINM -----END PGP SIGNATURE----- --=-wiZAOdaOZ9k1PKst0+gK-- --===============1915172290== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============1915172290==--