From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 1/3] drm/i915: Add get_config implementation for DSI encoder Date: Tue, 29 Jul 2014 14:38:36 +0300 Message-ID: <1406633916.9702.28.camel@intelbox> References: <1405165643-13189-1-git-send-email-shobhit.kumar@intel.com> <1405165643-13189-2-git-send-email-shobhit.kumar@intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0111303463==" Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 6A99C6E0C1 for ; Tue, 29 Jul 2014 04:38:39 -0700 (PDT) In-Reply-To: <1405165643-13189-2-git-send-email-shobhit.kumar@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Shobhit Kumar Cc: Jani Nikula , Daniel Vetter , intel-gfx List-Id: intel-gfx@lists.freedesktop.org --===============0111303463== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-C0mdJkIqt8UVfSCC7WEJ" --=-C0mdJkIqt8UVfSCC7WEJ Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Sat, 2014-07-12 at 17:17 +0530, Shobhit Kumar wrote: > Call to vlv_crtc_clock_get is not needed for DSI and was causing dpio > read WARN dumps as well. Absence of ->get_config was casuing othet WARN > dumps as well. With this the last of the known WARN dumps for DSI should > be fixed. >=20 > Signed-off-by: Shobhit Kumar > --- > drivers/gpu/drm/i915/intel_display.c | 7 +++--- > drivers/gpu/drm/i915/intel_dsi.c | 45 ++++++++++++++++++++++++++++++= ++++++ > drivers/gpu/drm/i915/intel_dsi.h | 3 +++ > drivers/gpu/drm/i915/intel_dsi_pll.c | 4 +++- > 4 files changed, 55 insertions(+), 4 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index fe6f1db..3d0ea7c 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -6309,9 +6309,10 @@ static bool i9xx_get_pipe_config(struct intel_crtc= *crtc, > =20 > if (IS_CHERRYVIEW(dev)) > chv_crtc_clock_get(crtc, pipe_config); > - else if (IS_VALLEYVIEW(dev)) > - vlv_crtc_clock_get(crtc, pipe_config); > - else > + else if (IS_VALLEYVIEW(dev)) { > + if (!intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI)) > + vlv_crtc_clock_get(crtc, pipe_config); > + } else > i9xx_crtc_clock_get(crtc, pipe_config); > =20 > return true; > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/inte= l_dsi.c > index bfcefbf..61da0e5 100644 > --- a/drivers/gpu/drm/i915/intel_dsi.c > +++ b/drivers/gpu/drm/i915/intel_dsi.c > @@ -351,9 +351,54 @@ static bool intel_dsi_get_hw_state(struct intel_enco= der *encoder, > static void intel_dsi_get_config(struct intel_encoder *encoder, > struct intel_crtc_config *pipe_config) > { > + struct drm_i915_private *dev_priv =3D encoder->base.dev->dev_private; > + struct intel_dsi *intel_dsi =3D enc_to_intel_dsi(&encoder->base); > + u32 dsi_clock, pclk; > + u32 pll_ctl, pll_div; > + u32 m =3D 0, p =3D 0; > + int refclk =3D 25000; > + int i; > + > DRM_DEBUG_KMS("\n"); > =20 > /* XXX: read flags, set to adjusted_mode */ This comment can be removed. > + pipe_config->quirks =3D 1; The proper macro should be used. > + > + memset(&pipe_config->dpll_hw_state, 0, > + sizeof(pipe_config->dpll_hw_state)); > + > + mutex_lock(&dev_priv->dpio_lock); > + pll_ctl =3D vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); > + pll_div =3D vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); > + mutex_unlock(&dev_priv->dpio_lock); > + > + pll_ctl &=3D ~(DSI_PLL_CLK_GATE_DSI0_DSIPLL | DSI_PLL_VCO_EN); > + pll_ctl =3D pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2); I'd prefer a proper masking of the P1 field instead of depending on other register fields being 0. The same goes for pll_div[M1]. > + > + while (pll_ctl) { > + pll_ctl =3D pll_ctl >> 1; > + p++; > + } > + p--; > + > + for (i =3D 0; i < num_lfsr_converts; i++) { > + if (lfsr_converts[i] =3D=3D pll_div) > + break; > + } > + > + if (i =3D=3D num_lfsr_converts) { > + DRM_ERROR("wrong m_seed programmed\n"); > + return; > + } > + > + m =3D i + 62; > + > + dsi_clock =3D (m * refclk) / p; Should guard against div-by-zero. > + pclk =3D DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, > + pipe_config->pipe_bpp); dsi_clk_from_pclk() uses dsi->pixel_format in place of pipe_bpp, so an assert here that the two values agree would be nice. > + > + pipe_config->adjusted_mode.crtc_clock =3D pclk; > + pipe_config->port_clock =3D pclk; > } > =20 > static enum drm_mode_status > diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/inte= l_dsi.h > index 31db33d..e0c16b0 100644 > --- a/drivers/gpu/drm/i915/intel_dsi.h > +++ b/drivers/gpu/drm/i915/intel_dsi.h > @@ -130,6 +130,9 @@ static inline struct intel_dsi *enc_to_intel_dsi(stru= ct drm_encoder *encoder) > return container_of(encoder, struct intel_dsi, base.base); > } > =20 > +extern const u32 lfsr_converts[]; > +extern const int num_lfsr_converts; > + > extern void vlv_enable_dsi_pll(struct intel_encoder *encoder); > extern void vlv_disable_dsi_pll(struct intel_encoder *encoder); > =20 > diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/= intel_dsi_pll.c > index ba79ec1..78449ea 100644 > --- a/drivers/gpu/drm/i915/intel_dsi_pll.c > +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c > @@ -43,13 +43,15 @@ struct dsi_mnp { > u32 dsi_pll_div; > }; > =20 > -static const u32 lfsr_converts[] =3D { > +const u32 lfsr_converts[] =3D { > 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */ > 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */ > 106, 53, 282, 397, 354, 227, 113, 56, 284, 142, /* 81 - 90 */ > 71, 35 /* 91 - 92 */ > }; > =20 > +const int num_lfsr_converts =3D sizeof(lfsr_converts) / sizeof(lfsr_conv= erts[0]); You can use ARRAY_SIZE here. > + > #ifdef DSI_CLK_FROM_RR > =20 > static u32 dsi_rr_formula(const struct drm_display_mode *mode, --=-C0mdJkIqt8UVfSCC7WEJ Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJT14e8AAoJEORIIAnNuWDFqBwIAIBCnZjxSEtx2sQBfEnljYDB uNk3uq44KyvaJc/gEND76eMHONjyWTPGIDlYsZ1j86mN0jiYxZeQogItD71Vp9qJ FDyRUszaRcqp2vBwzYjYCktrZK1U2neXdBMBnfCaUr460Es8nU6+xLZg5eClljAb X1e1j/oFjT0LjMGsP9var/895GRlXTSp+/GEFHvZpApHcT9oS2G2fa88bF+8xxfG 90sdDc9SBiM1nxNMoDiHSWTrxkECoFom5HVR1y5sNkIgZezNMEMf3bohgEtrjPjy 7HHL/umOal//+aFHK+BoD9icnxpy4G09Puf8PIpHbAKo1sWPk0Gt3YhZK0a59Y0= =XiY2 -----END PGP SIGNATURE----- --=-C0mdJkIqt8UVfSCC7WEJ-- --===============0111303463== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0111303463==--