From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 2/3] drm/i915: wait for all DSI FIFOs to be empty Date: Tue, 29 Jul 2014 15:30:25 +0300 Message-ID: <1406637025.9702.42.camel@intelbox> References: <1405165643-13189-1-git-send-email-shobhit.kumar@intel.com> <1405165643-13189-3-git-send-email-shobhit.kumar@intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1654777648==" Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id D29846E173 for ; Tue, 29 Jul 2014 05:30:28 -0700 (PDT) In-Reply-To: <1405165643-13189-3-git-send-email-shobhit.kumar@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Shobhit Kumar Cc: Jani Nikula , Daniel Vetter , intel-gfx List-Id: intel-gfx@lists.freedesktop.org --===============1654777648== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-CxMrGnY24cexrpxbbSjh" --=-CxMrGnY24cexrpxbbSjh Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Sat, 2014-07-12 at 17:17 +0530, Shobhit Kumar wrote: > Ensure that the DSI packets for a particular sequence are completely > sent before going ahead in the enabling or disabling of the panel >=20 > Signed-off-by: Shobhit Kumar Reviewed-by: Imre Deak > --- > drivers/gpu/drm/i915/intel_dsi.c | 8 ++++++++ > drivers/gpu/drm/i915/intel_dsi_cmd.c | 16 ++++++++++++++++ > drivers/gpu/drm/i915/intel_dsi_cmd.h | 1 + > 3 files changed, 25 insertions(+) >=20 > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/inte= l_dsi.c > index 61da0e5..98c78ab 100644 > --- a/drivers/gpu/drm/i915/intel_dsi.c > +++ b/drivers/gpu/drm/i915/intel_dsi.c > @@ -152,6 +152,8 @@ static void intel_dsi_enable(struct intel_encoder *en= coder) > if (intel_dsi->dev.dev_ops->enable) > intel_dsi->dev.dev_ops->enable(&intel_dsi->dev); > =20 > + wait_for_dsi_fifo_empty(intel_dsi); > + > /* assert ip_tg_enable signal */ > temp =3D I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK; > temp =3D temp | intel_dsi->port_bits; > @@ -192,6 +194,8 @@ static void intel_dsi_pre_enable(struct intel_encoder= *encoder) > if (intel_dsi->dev.dev_ops->send_otp_cmds) > intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev); > =20 > + wait_for_dsi_fifo_empty(intel_dsi); > + > /* Enable port in pre-enable phase itself because as per hw team > * recommendation, port should be enabled befor plane & pipe */ > intel_dsi_enable(encoder); > @@ -232,6 +236,8 @@ static void intel_dsi_disable(struct intel_encoder *e= ncoder) > DRM_DEBUG_KMS("\n"); > =20 > if (is_vid_mode(intel_dsi)) { > + wait_for_dsi_fifo_empty(intel_dsi); > + > /* de-assert ip_tg_enable signal */ > temp =3D I915_READ(MIPI_PORT_CTRL(pipe)); > I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE); > @@ -261,6 +267,8 @@ static void intel_dsi_disable(struct intel_encoder *e= ncoder) > * some next enable sequence send turn on packet error is observed */ > if (intel_dsi->dev.dev_ops->disable) > intel_dsi->dev.dev_ops->disable(&intel_dsi->dev); > + > + wait_for_dsi_fifo_empty(intel_dsi); > } > =20 > static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) > diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/= intel_dsi_cmd.c > index 933c863..7f1430a 100644 > --- a/drivers/gpu/drm/i915/intel_dsi_cmd.c > +++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c > @@ -419,3 +419,19 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cm= d, bool hs) > =20 > return 0; > } > + > +void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi) > +{ > + struct drm_encoder *encoder =3D &intel_dsi->base.base; > + struct drm_device *dev =3D encoder->dev; > + struct drm_i915_private *dev_priv =3D dev->dev_private; > + struct intel_crtc *intel_crtc =3D to_intel_crtc(encoder->crtc); > + enum pipe pipe =3D intel_crtc->pipe; > + u32 mask; > + > + mask =3D LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | > + LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; > + > + if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) =3D=3D mask, = 100)) > + DRM_ERROR("DPI FIFOs are not empty\n"); > +} > diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.h b/drivers/gpu/drm/i915/= intel_dsi_cmd.h > index 9a18cbf..46aa1ac 100644 > --- a/drivers/gpu/drm/i915/intel_dsi_cmd.h > +++ b/drivers/gpu/drm/i915/intel_dsi_cmd.h > @@ -51,6 +51,7 @@ int dsi_vc_generic_read(struct intel_dsi *intel_dsi, in= t channel, > u8 *reqdata, int reqlen, u8 *buf, int buflen); > =20 > int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs); > +void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi); > =20 > /* XXX: questionable write helpers */ > static inline int dsi_vc_dcs_write_0(struct intel_dsi *intel_dsi, --=-CxMrGnY24cexrpxbbSjh Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJT15PhAAoJEORIIAnNuWDFltQIANS2DK2FyK2F1EXa240GNmT2 l9Bm5DL5bp3SnUeCAhckrlm1mKX24Xw85YYpSE9ypG8ztScsq6IeGGrMhBMgvGM1 iO1e+VXtfbVeALRFHoH2+yhjD0iCXvwPGLByqaGx8WDZi/i7URmIDwFZRuMxe2D3 kO7SL29qDN18oD0jbxT8l/yMh6jUSv/b8XJ6TmSgzmtEJ2RpdnXzsxJqUIXOheP5 5TPidPsIdBn23Qe+Yfu7qA4jbXiJaU8rmobPdKejqTCKy0mZotMu+k7t+GCsNt4i IQUcQyoVE+fmQydN81kO+noUXEo+RqHadqrNKntWWwf/3SuigQvAC7qANympgyw= =FQJN -----END PGP SIGNATURE----- --=-CxMrGnY24cexrpxbbSjh-- --===============1654777648== Content-Type: text/plain; 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