From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 3/3] drm/i915: Add sprite watermark programming for VLV and CHV Date: Thu, 31 Jul 2014 16:44:35 +0300 Message-ID: <1406814275.18327.34.camel@intelbox> References: <1405515245-14946-1-git-send-email-gajanan.bhat@intel.com> <1405515245-14946-4-git-send-email-gajanan.bhat@intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1911722370==" Return-path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 282636E441 for ; Thu, 31 Jul 2014 06:44:43 -0700 (PDT) In-Reply-To: <1405515245-14946-4-git-send-email-gajanan.bhat@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Gajanan Bhat Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============1911722370== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-IPIBTayuy3P59ik/FqMg" --=-IPIBTayuy3P59ik/FqMg Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 2014-07-16 at 18:24 +0530, Gajanan Bhat wrote: > Program DDL register as part sprite watermark programming for CHV and VLV= . >=20 > Signed-off-by: Gajanan Bhat This looks ok, but could you confirm, ideally referencing some document, that we don't need to program any of the sprite watermark level registers along with the DDL values? Specifically I mean the FW7, FW8 registers. --Imre > --- > drivers/gpu/drm/i915/intel_pm.c | 44 +++++++++++++++++++++++++++++++++= ++++++ > 1 file changed, 44 insertions(+) >=20 > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index f3a3e90..0f439f7 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -1405,6 +1405,48 @@ static void valleyview_update_wm(struct drm_crtc *= crtc) > intel_set_memory_cxsr(dev_priv, true); > } > =20 > +static void valleyview_update_sprite_wm(struct drm_plane *plane, > + struct drm_crtc *crtc, > + uint32_t sprite_width, > + uint32_t sprite_height, > + int pixel_size, > + bool enabled, bool scaled) > +{ > + struct drm_device *dev =3D crtc->dev; > + struct drm_i915_private *dev_priv =3D dev->dev_private; > + int pipe =3D to_intel_plane(plane)->pipe; > + int drain_latency; > + int plane_prec; > + int sprite_dl; > + int prec_mult; > + > + if (to_intel_plane(plane)->plane =3D=3D 0) > + sprite_dl =3D I915_READ(VLV_DDL(pipe)) & ~DDL_SPRITE0_PRECISION_64 & > + ~(DRAIN_LATENCY_MAX << DDL_SPRITE0_SHIFT); > + else > + sprite_dl =3D I915_READ(VLV_DDL(pipe)) & ~DDL_SPRITE1_PRECISION_64 & > + ~(DRAIN_LATENCY_MAX << DDL_SPRITE1_SHIFT); > + > + if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, > + &drain_latency)) { > + if (to_intel_plane(plane)->plane =3D=3D 0) { > + plane_prec =3D (prec_mult =3D=3D DRAIN_LATENCY_PRECISION_64) ? > + DDL_SPRITE0_PRECISION_64 : > + DDL_SPRITE0_PRECISION_32; > + sprite_dl =3D sprite_dl | plane_prec | > + drain_latency << DDL_SPRITE0_SHIFT; > + } else { > + plane_prec =3D (prec_mult =3D=3D DRAIN_LATENCY_PRECISION_64) ? > + DDL_SPRITE1_PRECISION_64 : > + DDL_SPRITE1_PRECISION_32; > + sprite_dl =3D sprite_dl | plane_prec | > + drain_latency << DDL_SPRITE1_SHIFT; > + } > + } > + > + I915_WRITE(VLV_DDL(pipe), sprite_dl); > +} > + > static void g4x_update_wm(struct drm_crtc *crtc) > { > struct drm_device *dev =3D crtc->dev; > @@ -6851,10 +6893,12 @@ void intel_init_pm(struct drm_device *dev) > dev_priv->display.init_clock_gating =3D gen8_init_clock_gating; > } else if (IS_CHERRYVIEW(dev)) { > dev_priv->display.update_wm =3D valleyview_update_wm; > + dev_priv->display.update_sprite_wm =3D valleyview_update_sprite_wm; > dev_priv->display.init_clock_gating =3D > cherryview_init_clock_gating; > } else if (IS_VALLEYVIEW(dev)) { > dev_priv->display.update_wm =3D valleyview_update_wm; > + dev_priv->display.update_sprite_wm =3D valleyview_update_sprite_wm; > dev_priv->display.init_clock_gating =3D > valleyview_init_clock_gating; > } else if (IS_PINEVIEW(dev)) { --=-IPIBTayuy3P59ik/FqMg Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJT2khDAAoJEORIIAnNuWDFOmAIANp5ufpBvA/aWjUZbHVDiShH Gn1I6bfKa8xMdFRYbO6talAcnb/pC21QnU8sVeB18ZysX420ukCUYH54CGc3jjOv 9qiJRAqWVu8U84/fdBTgvrVl1ix6N7zWCgVL7xYBaqXSXNBpHvi8QAled8pEbDSa Zd1CCin+g0jRn2ExJlbTWehVnH0ePw8R2K7I/p8iLeSU6ES8h7q9px+q4cXK5dHK qcWYJvJEMT3KfnoB4u+l9iBHV7K5VJ550fkccTIP8UNyApdILs/4+WqDqp13SxL7 T+5TU3BpoT7Y08YwSdwHe+ok+iWzuX0a0o2X2VooW4qC3QFiVn+cV7L2+hGRoyE= =xw9e -----END PGP SIGNATURE----- --=-IPIBTayuy3P59ik/FqMg-- --===============1911722370== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============1911722370==--