From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 3/3] drm/i915: Add sprite watermark programming for VLV and CHV Date: Thu, 07 Aug 2014 12:51:51 +0300 Message-ID: <1407405111.32060.16.camel@intelbox> References: <1405515245-14946-1-git-send-email-gajanan.bhat@intel.com> <1405515245-14946-4-git-send-email-gajanan.bhat@intel.com> <1406814275.18327.34.camel@intelbox> <53E31517.6090204@intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1789935895==" Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id E45CA6E064 for ; Thu, 7 Aug 2014 02:51:53 -0700 (PDT) In-Reply-To: <53E31517.6090204@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "Bhat, Gajanan" Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============1789935895== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-0KLpOvsaa5ZS5D4Fn2y2" --=-0KLpOvsaa5ZS5D4Fn2y2 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, 2014-08-07 at 11:26 +0530, Bhat, Gajanan wrote: > On 7/31/2014 7:14 PM, Imre Deak wrote: > > On Wed, 2014-07-16 at 18:24 +0530, Gajanan Bhat wrote: > >> Program DDL register as part sprite watermark programming for CHV and = VLV. > >> > >> Signed-off-by: Gajanan Bhat > > This looks ok, but could you confirm, ideally referencing some document= , > > that we don't need to program any of the sprite watermark level > > registers along with the DDL values? Specifically I mean the FW7, FW8 > > registers. > > > I have looked at the B-spec to again confirm my understanding. The > chicken bit in CBR1 specifies which mechanism (PND or watermark) to be > used. In our case we are using only the PND with DDL. I couldn't find > any reference which explicitly tells that both DDL and watermarks > should be programmed together. Also we have tested this code and so far > it has not caused any problem. Thanks for clarifying this, the docs on this are fuzzy to me. Earlier Cesar and Ville also pointed out that the PND mechanism depends on the MI_ARB[trickle feed] flag being enabled, which is afaics disabled on VLV. But based on what you say I understand that the DDL values are not used in the 'watermark mode', so I'm ok with your change. Perhaps a comment about this could be added. --Imre > -Gajanan >=20 > >> --- > >> drivers/gpu/drm/i915/intel_pm.c | 44 +++++++++++++++++++++++++++++= ++++++++++ > >> 1 file changed, 44 insertions(+) > >> > >> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/in= tel_pm.c > >> index f3a3e90..0f439f7 100644 > >> --- a/drivers/gpu/drm/i915/intel_pm.c > >> +++ b/drivers/gpu/drm/i915/intel_pm.c > >> @@ -1405,6 +1405,48 @@ static void valleyview_update_wm(struct drm_crt= c *crtc) > >> intel_set_memory_cxsr(dev_priv, true); > >> } > >> =20 > >> +static void valleyview_update_sprite_wm(struct drm_plane *plane, > >> + struct drm_crtc *crtc, > >> + uint32_t sprite_width, > >> + uint32_t sprite_height, > >> + int pixel_size, > >> + bool enabled, bool scaled) > >> +{ > >> + struct drm_device *dev =3D crtc->dev; > >> + struct drm_i915_private *dev_priv =3D dev->dev_private; > >> + int pipe =3D to_intel_plane(plane)->pipe; > >> + int drain_latency; > >> + int plane_prec; > >> + int sprite_dl; > >> + int prec_mult; > >> + > >> + if (to_intel_plane(plane)->plane =3D=3D 0) > >> + sprite_dl =3D I915_READ(VLV_DDL(pipe)) & ~DDL_SPRITE0_PRECISION_64 = & > >> + ~(DRAIN_LATENCY_MAX << DDL_SPRITE0_SHIFT); > >> + else > >> + sprite_dl =3D I915_READ(VLV_DDL(pipe)) & ~DDL_SPRITE1_PRECISION_64 = & > >> + ~(DRAIN_LATENCY_MAX << DDL_SPRITE1_SHIFT); > >> + > >> + if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mul= t, > >> + &drain_latency)) { > >> + if (to_intel_plane(plane)->plane =3D=3D 0) { > >> + plane_prec =3D (prec_mult =3D=3D DRAIN_LATENCY_PRECISION_64) ? > >> + DDL_SPRITE0_PRECISION_64 : > >> + DDL_SPRITE0_PRECISION_32; > >> + sprite_dl =3D sprite_dl | plane_prec | > >> + drain_latency << DDL_SPRITE0_SHIFT; > >> + } else { > >> + plane_prec =3D (prec_mult =3D=3D DRAIN_LATENCY_PRECISION_64) ? > >> + DDL_SPRITE1_PRECISION_64 : > >> + DDL_SPRITE1_PRECISION_32; > >> + sprite_dl =3D sprite_dl | plane_prec | > >> + drain_latency << DDL_SPRITE1_SHIFT; > >> + } > >> + } > >> + > >> + I915_WRITE(VLV_DDL(pipe), sprite_dl); > >> +} > >> + > >> static void g4x_update_wm(struct drm_crtc *crtc) > >> { > >> struct drm_device *dev =3D crtc->dev; > >> @@ -6851,10 +6893,12 @@ void intel_init_pm(struct drm_device *dev) > >> dev_priv->display.init_clock_gating =3D gen8_init_clock_gating; > >> } else if (IS_CHERRYVIEW(dev)) { > >> dev_priv->display.update_wm =3D valleyview_update_wm; > >> + dev_priv->display.update_sprite_wm =3D valleyview_update_sprite_wm; > >> dev_priv->display.init_clock_gating =3D > >> cherryview_init_clock_gating; > >> } else if (IS_VALLEYVIEW(dev)) { > >> dev_priv->display.update_wm =3D valleyview_update_wm; > >> + dev_priv->display.update_sprite_wm =3D valleyview_update_sprite_wm; > >> dev_priv->display.init_clock_gating =3D > >> valleyview_init_clock_gating; > >> } else if (IS_PINEVIEW(dev)) { >=20 --=-0KLpOvsaa5ZS5D4Fn2y2 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJT40w3AAoJEORIIAnNuWDF1QwIAKs2sKsSJt6W/Z0HAOyacNSA iCJc5CI/4OWn5nec9SYhurIq+E3/o65m49fVl22sh6yC6D9ve8a/752qZAG+OSCy +s0HcwMkZLsRz4ZjO3doAgJQ70e9FxDWqFbFRWnoyt3zX64Bz00d93nXGxwbMocT FytJo6fGt+QyHeV7qL8h3c6IpBZILzc0rZ5FWe52wNtMp3u/s+9zbwFUKe+3oldM Nm+qkfu9Df0TFM++nrmNBk++IyOZGBcyIVzdmcdTMCebv06BjrkGQmYKh/fhWZMB ZfJha2ZPIXZe4alLvEd1Ea9cFVQJgmdg5idLp/210gdDMaxqCF2ti8cyaZQbyas= =WB7z -----END PGP SIGNATURE----- --=-0KLpOvsaa5ZS5D4Fn2y2-- --===============1789935895== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============1789935895==--