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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from DM4PR11MB5341.namprd11.prod.outlook.com (2603:10b6:5:390::22) by IA1PR11MB6121.namprd11.prod.outlook.com (2603:10b6:208:3ef::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8678.27; Wed, 7 May 2025 08:27:37 +0000 Received: from DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::397:7566:d626:e839]) by DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::397:7566:d626:e839%2]) with mapi id 15.20.8699.026; Wed, 7 May 2025 08:27:37 +0000 Message-ID: <1407e267-5ef7-43a5-b818-0b905c912102@intel.com> Date: Wed, 7 May 2025 13:57:31 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 07/17] drm/i915/vrr: Add DC Balance params to crtc_state To: Mitul Golani , , CC: References: <20250506145517.4129419-1-mitulkumar.ajitkumar.golani@intel.com> <20250506145517.4129419-8-mitulkumar.ajitkumar.golani@intel.com> Content-Language: en-US From: "Nautiyal, Ankit K" In-Reply-To: <20250506145517.4129419-8-mitulkumar.ajitkumar.golani@intel.com> Content-Type: text/plain; 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(Ankit) > > --v4: > - Update commit message and header. (Ankit) > - Add +1 to VMIN and VMAX only when it is non-zero. (Ankit) > > Signed-off-by: Mitul Golani Reviewed-by: Ankit Nautiyal > --- > drivers/gpu/drm/i915/display/intel_display.c | 8 +++++++ > .../drm/i915/display/intel_display_types.h | 7 ++++++ > drivers/gpu/drm/i915/display/intel_vrr.c | 24 +++++++++++++++++++ > 3 files changed, 39 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 287110e4e435..20c7c6eb485d 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -5412,6 +5412,14 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, > PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); > PIPE_CONF_CHECK_LLI(cmrr.cmrr_n); > PIPE_CONF_CHECK_BOOL(cmrr.enable); > + PIPE_CONF_CHECK_BOOL(vrr.dc_balance.enable); > + PIPE_CONF_CHECK_I(vrr.dc_balance.vmin); > + PIPE_CONF_CHECK_I(vrr.dc_balance.vmax); > + PIPE_CONF_CHECK_I(vrr.dc_balance.guardband); > + PIPE_CONF_CHECK_I(vrr.dc_balance.slope); > + PIPE_CONF_CHECK_I(vrr.dc_balance.max_increase); > + PIPE_CONF_CHECK_I(vrr.dc_balance.max_decrease); > + PIPE_CONF_CHECK_I(vrr.dc_balance.vblank_target); > } > > if (!fastset || intel_vrr_always_use_vrr_tg(display)) { > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index 7415564d058a..e6b5bec748cd 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1308,6 +1308,13 @@ struct intel_crtc_state { > u8 pipeline_full; > u16 flipline, vmin, vmax, guardband; > u32 vsync_end, vsync_start; > + struct { > + bool enable; > + u16 vmin, vmax; > + u16 guardband, slope; > + u16 max_increase, max_decrease; > + u16 vblank_target; > + } dc_balance; > } vrr; > > /* Content Match Refresh Rate state */ > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c > index ab4f8def821c..726fa49558d1 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -10,6 +10,7 @@ > #include "intel_de.h" > #include "intel_display_types.h" > #include "intel_dp.h" > +#include "intel_dmc_regs.h" > #include "intel_vrr.h" > #include "intel_vrr_regs.h" > > @@ -676,6 +677,8 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) > { > struct intel_display *display = to_intel_display(crtc_state); > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > + enum pipe pipe = crtc->pipe; > u32 trans_vrr_ctl, trans_vrr_vsync; > bool vrr_enable; > > @@ -738,6 +741,27 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) > else > crtc_state->vrr.enable = vrr_enable; > > + if (HAS_VRR_DC_BALANCE(display)) { > + crtc_state->vrr.dc_balance.enable = > + intel_de_read(display, PIPEDMC_DCB_CTL(pipe)) & PIPEDMC_ADAPTIVE_DCB_ENABLE; > + crtc_state->vrr.dc_balance.vmin = > + intel_de_read(display, PIPEDMC_DCB_VMIN(pipe)) ? > + intel_de_read(display, PIPEDMC_DCB_VMIN(pipe)) + 1 : 0; > + crtc_state->vrr.dc_balance.vmax = > + intel_de_read(display, PIPEDMC_DCB_VMAX(pipe)) ? > + intel_de_read(display, PIPEDMC_DCB_VMAX(pipe)) + 1 : 0; > + crtc_state->vrr.dc_balance.guardband = > + intel_de_read(display, PIPEDMC_DCB_GUARDBAND(pipe)); > + crtc_state->vrr.dc_balance.max_increase = > + intel_de_read(display, PIPEDMC_DCB_MAX_INCREASE(pipe)); > + crtc_state->vrr.dc_balance.max_decrease = > + intel_de_read(display, PIPEDMC_DCB_MAX_DECREASE(pipe)); > + crtc_state->vrr.dc_balance.slope = > + intel_de_read(display, PIPEDMC_DCB_SLOPE(pipe)); > + crtc_state->vrr.dc_balance.vblank_target = > + intel_de_read(display, PIPEDMC_DCB_VBLANK(pipe)); > + } > + > /* > * #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags. > * Since CMRR is currently disabled, set this flag for VRR for now.