From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH v2 09/14] drm/i915: Fix edp vdd locking Date: Tue, 02 Sep 2014 16:07:07 +0300 Message-ID: <1409663227.15662.6.camel@intelbox> References: <1408389369-22898-10-git-send-email-ville.syrjala@linux.intel.com> <1408469554-11625-1-git-send-email-ville.syrjala@linux.intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1972834830==" Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id A97476E47E for ; Tue, 2 Sep 2014 06:09:05 -0700 (PDT) In-Reply-To: <1408469554-11625-1-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============1972834830== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-T8O3FUUn7M6ONfHJIXEH" --=-T8O3FUUn7M6ONfHJIXEH Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, 2014-08-19 at 20:32 +0300, ville.syrjala@linux.intel.com wrote: > From: Ville Syrj=C3=A4l=C3=A4 >=20 > Introduce a new mutex (pps_mutex) to protect the power sequencer > state. For now this state includes want_panel_vdd as well as the > power sequencer registers. >=20 > We need a single mutex (as opposed to per port) because later on we > will need to deal with VLV/CHV which have multiple power sequencer > which can be reassigned to different ports. >=20 > v2: Add the locking to intel_dp_encoder_suspend too (Imre) >=20 > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 > --- > drivers/gpu/drm/i915/i915_drv.h | 3 ++ > drivers/gpu/drm/i915/intel_display.c | 2 + > drivers/gpu/drm/i915/intel_dp.c | 99 ++++++++++++++++++++++++++++++= ++---- > 3 files changed, 93 insertions(+), 11 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_= drv.h > index 6fbd316..c5faefb 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1501,6 +1501,9 @@ struct drm_i915_private { > /* LVDS info */ > bool no_aux_handshake; > =20 > + /* protects panel power sequencer state */ > + struct mutex pps_mutex; > + > struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 96= 5 */ > int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ > int num_fence_regs; /* 8 on pre-965, 16 otherwise */ > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index 0b327eb..ff86729 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -12437,6 +12437,8 @@ static void intel_init_display(struct drm_device = *dev) > } > =20 > intel_panel_init_backlight_funcs(dev); > + > + mutex_init(&dev_priv->pps_mutex); > } > =20 > /* > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel= _dp.c > index 9efa6bf..446df28 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -300,6 +300,8 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp) > enum port port =3D intel_dig_port->port; > enum pipe pipe; > =20 > + lockdep_assert_held(&dev_priv->pps_mutex); > + > /* modeset should have pipe */ > if (crtc) > return to_intel_crtc(crtc)->pipe; > @@ -352,6 +354,8 @@ static int edp_notify_handler(struct notifier_block *= this, unsigned long code, > if (!IS_VALLEYVIEW(dev) || !is_edp(intel_dp) || code !=3D SYS_RESTART) > return 0; > =20 > + mutex_lock(&dev_priv->pps_mutex); > + This needs rebasing since 02/14 wasn't applied. > pipe =3D vlv_power_sequencer_pipe(intel_dp); > =20 > pp_ctrl_reg =3D VLV_PIPE_PP_CONTROL(pipe); > @@ -364,6 +368,8 @@ static int edp_notify_handler(struct notifier_block *= this, unsigned long code, > I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); > msleep(intel_dp->panel_power_cycle_delay); > =20 > + mutex_unlock(&dev_priv->pps_mutex); > + > return 0; > } > =20 > @@ -372,6 +378,8 @@ static bool edp_have_panel_power(struct intel_dp *int= el_dp) > struct drm_device *dev =3D intel_dp_to_dev(intel_dp); > struct drm_i915_private *dev_priv =3D dev->dev_private; > =20 > + lockdep_assert_held(&dev_priv->pps_mutex); > + > return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) !=3D 0; > } > =20 > @@ -383,6 +391,8 @@ static bool edp_have_panel_vdd(struct intel_dp *intel= _dp) > struct intel_encoder *intel_encoder =3D &intel_dig_port->base; > enum intel_display_power_domain power_domain; > =20 > + lockdep_assert_held(&dev_priv->pps_mutex); > + > power_domain =3D intel_display_port_power_domain(intel_encoder); > return intel_display_power_enabled(dev_priv, power_domain) && > (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) !=3D 0; > @@ -533,6 +543,8 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, > bool has_aux_irq =3D HAS_AUX_IRQ(dev); > bool vdd; > =20 > + mutex_lock(&dev_priv->pps_mutex); > + > /* > * We will be called with VDD already enabled for dpcd/edid/oui reads. > * In such cases we want to leave VDD enabled and it's up to upper laye= rs > @@ -648,6 +660,8 @@ out: > if (vdd) > edp_panel_vdd_off(intel_dp, false); > =20 > + mutex_unlock(&dev_priv->pps_mutex); > + > return ret; > } > =20 > @@ -1102,6 +1116,8 @@ static void wait_panel_status(struct intel_dp *inte= l_dp, > struct drm_i915_private *dev_priv =3D dev->dev_private; > u32 pp_stat_reg, pp_ctrl_reg; > =20 > + lockdep_assert_held(&dev_priv->pps_mutex); > + > pp_stat_reg =3D _pp_stat_reg(intel_dp); > pp_ctrl_reg =3D _pp_ctrl_reg(intel_dp); > =20 > @@ -1165,6 +1181,8 @@ static u32 ironlake_get_pp_control(struct intel_dp= *intel_dp) > struct drm_i915_private *dev_priv =3D dev->dev_private; > u32 control; > =20 > + lockdep_assert_held(&dev_priv->pps_mutex); > + > control =3D I915_READ(_pp_ctrl_reg(intel_dp)); > control &=3D ~PANEL_UNLOCK_MASK; > control |=3D PANEL_UNLOCK_REGS; > @@ -1182,6 +1200,8 @@ static bool edp_panel_vdd_on(struct intel_dp *intel= _dp) > u32 pp_stat_reg, pp_ctrl_reg; > bool need_to_disable =3D !intel_dp->want_panel_vdd; > =20 > + lockdep_assert_held(&dev_priv->pps_mutex); > + > if (!is_edp(intel_dp)) > return false; > =20 > @@ -1221,12 +1241,16 @@ static bool edp_panel_vdd_on(struct intel_dp *int= el_dp) > =20 > void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) > { > + struct drm_i915_private *dev_priv =3D > + intel_dp_to_dev(intel_dp)->dev_private; > bool vdd; > =20 > if (!is_edp(intel_dp)) > return; > =20 > + mutex_lock(&dev_priv->pps_mutex); > vdd =3D edp_panel_vdd_on(intel_dp); > + mutex_unlock(&dev_priv->pps_mutex); > =20 > WARN(!vdd, "eDP VDD already requested on\n"); > } > @@ -1242,7 +1266,7 @@ static void edp_panel_vdd_off_sync(struct intel_dp = *intel_dp) > u32 pp; > u32 pp_stat_reg, pp_ctrl_reg; > =20 > - WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); > + lockdep_assert_held(&dev_priv->pps_mutex); > =20 > WARN_ON(intel_dp->want_panel_vdd); > =20 > @@ -1275,12 +1299,13 @@ static void edp_panel_vdd_work(struct work_struct= *__work) > { > struct intel_dp *intel_dp =3D container_of(to_delayed_work(__work), > struct intel_dp, panel_vdd_work); > - struct drm_device *dev =3D intel_dp_to_dev(intel_dp); > + struct drm_i915_private *dev_priv =3D > + intel_dp_to_dev(intel_dp)->dev_private; > =20 > - drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); > + mutex_lock(&dev_priv->pps_mutex); > if (!intel_dp->want_panel_vdd) > edp_panel_vdd_off_sync(intel_dp); > - drm_modeset_unlock(&dev->mode_config.connection_mutex); > + mutex_unlock(&dev_priv->pps_mutex); > } > =20 > static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) > @@ -1298,6 +1323,11 @@ static void edp_panel_vdd_schedule_off(struct inte= l_dp *intel_dp) > =20 > static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) > { > + struct drm_i915_private *dev_priv =3D > + intel_dp_to_dev(intel_dp)->dev_private; > + > + lockdep_assert_held(&dev_priv->pps_mutex); > + > if (!is_edp(intel_dp)) > return; > =20 > @@ -1313,7 +1343,15 @@ static void edp_panel_vdd_off(struct intel_dp *int= el_dp, bool sync) > =20 > static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync= ) > { > + struct drm_i915_private *dev_priv =3D > + intel_dp_to_dev(intel_dp)->dev_private; > + > + if (!is_edp(intel_dp)) > + return; > + > + mutex_lock(&dev_priv->pps_mutex); > edp_panel_vdd_off(intel_dp, sync); > + mutex_unlock(&dev_priv->pps_mutex); > } > =20 > void intel_edp_panel_on(struct intel_dp *intel_dp) > @@ -1328,9 +1366,11 @@ void intel_edp_panel_on(struct intel_dp *intel_dp) > =20 > DRM_DEBUG_KMS("Turn eDP power on\n"); > =20 > + mutex_lock(&dev_priv->pps_mutex); > + > if (edp_have_panel_power(intel_dp)) { > DRM_DEBUG_KMS("eDP power already on\n"); > - return; > + goto out; > } > =20 > wait_panel_power_cycle(intel_dp); > @@ -1359,6 +1399,9 @@ void intel_edp_panel_on(struct intel_dp *intel_dp) > I915_WRITE(pp_ctrl_reg, pp); > POSTING_READ(pp_ctrl_reg); > } > + > + out: > + mutex_unlock(&dev_priv->pps_mutex); > } > =20 > void intel_edp_panel_off(struct intel_dp *intel_dp) > @@ -1376,6 +1419,8 @@ void intel_edp_panel_off(struct intel_dp *intel_dp) > =20 > DRM_DEBUG_KMS("Turn eDP power off\n"); > =20 > + mutex_lock(&dev_priv->pps_mutex); > + > WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); > =20 > pp =3D ironlake_get_pp_control(intel_dp); > @@ -1397,6 +1442,8 @@ void intel_edp_panel_off(struct intel_dp *intel_dp) > /* We got a reference when we enabled the VDD. */ > power_domain =3D intel_display_port_power_domain(intel_encoder); > intel_display_power_put(dev_priv, power_domain); > + > + mutex_unlock(&dev_priv->pps_mutex); > } > =20 > void intel_edp_backlight_on(struct intel_dp *intel_dp) > @@ -1421,6 +1468,9 @@ void intel_edp_backlight_on(struct intel_dp *intel_= dp) > * allowing it to appear. > */ > wait_backlight_on(intel_dp); > + > + mutex_lock(&dev_priv->pps_mutex); > + > pp =3D ironlake_get_pp_control(intel_dp); > pp |=3D EDP_BLC_ENABLE; > =20 > @@ -1428,6 +1478,8 @@ void intel_edp_backlight_on(struct intel_dp *intel_= dp) > =20 > I915_WRITE(pp_ctrl_reg, pp); > POSTING_READ(pp_ctrl_reg); > + > + mutex_unlock(&dev_priv->pps_mutex); > } > =20 > void intel_edp_backlight_off(struct intel_dp *intel_dp) > @@ -1440,6 +1492,8 @@ void intel_edp_backlight_off(struct intel_dp *intel= _dp) > if (!is_edp(intel_dp)) > return; > =20 > + mutex_lock(&dev_priv->pps_mutex); > + > DRM_DEBUG_KMS("\n"); > pp =3D ironlake_get_pp_control(intel_dp); > pp &=3D ~EDP_BLC_ENABLE; > @@ -1448,8 +1502,10 @@ void intel_edp_backlight_off(struct intel_dp *inte= l_dp) > =20 > I915_WRITE(pp_ctrl_reg, pp); > POSTING_READ(pp_ctrl_reg); > - intel_dp->last_backlight_off =3D jiffies; > =20 > + mutex_unlock(&dev_priv->pps_mutex); > + > + intel_dp->last_backlight_off =3D jiffies; > edp_wait_backlight_off(intel_dp); > =20 > intel_panel_disable_backlight(intel_dp->attached_connector); These need to be rebased on the latest backlight changes, moving the locking into _intel_edp_backlight_on/off() and adding it to intel_edp_backlight_power(). With the above things rebased the patch looks ok to me: Reviewed-by: Imre Deak > @@ -2182,9 +2238,11 @@ static void vlv_pre_enable_dp(struct intel_encoder= *encoder) > =20 > if (is_edp(intel_dp)) { > /* init power sequencer on this pipe and port */ > + mutex_lock(&dev_priv->pps_mutex); > intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); > intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, > &power_seq); > + mutex_unlock(&dev_priv->pps_mutex); > } > =20 > intel_enable_dp(encoder); > @@ -2284,9 +2342,11 @@ static void chv_pre_enable_dp(struct intel_encoder= *encoder) > =20 > if (is_edp(intel_dp)) { > /* init power sequencer on this pipe and port */ > + mutex_lock(&dev_priv->pps_mutex); > intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); > intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, > &power_seq); > + mutex_unlock(&dev_priv->pps_mutex); > } > =20 > intel_enable_dp(encoder); > @@ -4027,15 +4087,16 @@ void intel_dp_encoder_destroy(struct drm_encoder = *encoder) > struct intel_digital_port *intel_dig_port =3D enc_to_dig_port(encoder); > struct intel_dp *intel_dp =3D &intel_dig_port->dp; > struct drm_device *dev =3D intel_dp_to_dev(intel_dp); > + struct drm_i915_private *dev_priv =3D dev->dev_private; > =20 > drm_dp_aux_unregister(&intel_dp->aux); > intel_dp_mst_encoder_cleanup(intel_dig_port); > drm_encoder_cleanup(encoder); > if (is_edp(intel_dp)) { > cancel_delayed_work_sync(&intel_dp->panel_vdd_work); > - drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); > + mutex_lock(&dev_priv->pps_mutex); > edp_panel_vdd_off_sync(intel_dp); > - drm_modeset_unlock(&dev->mode_config.connection_mutex); > + mutex_unlock(&dev_priv->pps_mutex); > if (intel_dp->edp_notifier.notifier_call) { > unregister_reboot_notifier(&intel_dp->edp_notifier); > intel_dp->edp_notifier.notifier_call =3D NULL; > @@ -4047,11 +4108,15 @@ void intel_dp_encoder_destroy(struct drm_encoder = *encoder) > static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder= ) > { > struct intel_dp *intel_dp =3D enc_to_intel_dp(&intel_encoder->base); > + struct drm_device *dev =3D intel_dp_to_dev(intel_dp); > + struct drm_i915_private *dev_priv =3D dev->dev_private; > =20 > if (!is_edp(intel_dp)) > return; > =20 > + mutex_lock(&dev_priv->pps_mutex); > edp_panel_vdd_off_sync(intel_dp); > + mutex_unlock(&dev_priv->pps_mutex); > } > =20 > static void intel_dp_encoder_reset(struct drm_encoder *encoder) > @@ -4232,6 +4297,8 @@ intel_dp_init_panel_power_sequencer(struct drm_devi= ce *dev, > u32 pp_on, pp_off, pp_div, pp; > int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; > =20 > + lockdep_assert_held(&dev_priv->pps_mutex); > + > if (HAS_PCH_SPLIT(dev)) { > pp_ctrl_reg =3D PCH_PP_CONTROL; > pp_on_reg =3D PCH_PP_ON_DELAYS; > @@ -4333,6 +4400,8 @@ intel_dp_init_panel_power_sequencer_registers(struc= t drm_device *dev, > int pp_on_reg, pp_off_reg, pp_div_reg; > enum port port =3D dp_to_dig_port(intel_dp)->port; > =20 > + lockdep_assert_held(&dev_priv->pps_mutex); > + > if (HAS_PCH_SPLIT(dev)) { > pp_on_reg =3D PCH_PP_ON_DELAYS; > pp_off_reg =3D PCH_PP_OFF_DELAYS; > @@ -4525,9 +4594,11 @@ void intel_edp_panel_vdd_sanitize(struct intel_enc= oder *intel_encoder) > if (intel_encoder->type !=3D INTEL_OUTPUT_EDP) > return; > =20 > + mutex_lock(&dev_priv->pps_mutex); > + > intel_dp =3D enc_to_intel_dp(&intel_encoder->base); > if (!edp_have_panel_vdd(intel_dp)) > - return; > + goto out; > /* > * The VDD bit needs a power domain reference, so if the bit is > * already enabled when we boot or resume, grab this reference and > @@ -4539,6 +4610,8 @@ void intel_edp_panel_vdd_sanitize(struct intel_enco= der *intel_encoder) > intel_display_power_get(dev_priv, power_domain); > =20 > edp_panel_vdd_schedule_off(intel_dp); > + out: > + mutex_unlock(&dev_priv->pps_mutex); > } > =20 > static bool intel_edp_init_connector(struct intel_dp *intel_dp, > @@ -4580,7 +4653,9 @@ static bool intel_edp_init_connector(struct intel_d= p *intel_dp, > } > =20 > /* We now know it's not a ghost, init power sequence regs. */ > + mutex_lock(&dev_priv->pps_mutex); > intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq)= ; > + mutex_unlock(&dev_priv->pps_mutex); > =20 > mutex_lock(&dev->mode_config.mutex); > edid =3D drm_get_edid(connector, &intel_dp->aux.ddc); > @@ -4712,8 +4787,10 @@ intel_dp_init_connector(struct intel_digital_port = *intel_dig_port, > } > =20 > if (is_edp(intel_dp)) { > + mutex_lock(&dev_priv->pps_mutex); > intel_dp_init_panel_power_timestamps(intel_dp); > intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); > + mutex_unlock(&dev_priv->pps_mutex); > } > =20 > intel_dp_aux_init(intel_dp, intel_connector); > @@ -4729,9 +4806,9 @@ intel_dp_init_connector(struct intel_digital_port *= intel_dig_port, > drm_dp_aux_unregister(&intel_dp->aux); > if (is_edp(intel_dp)) { > cancel_delayed_work_sync(&intel_dp->panel_vdd_work); > - drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); > + mutex_lock(&dev_priv->pps_mutex); > edp_panel_vdd_off_sync(intel_dp); > - drm_modeset_unlock(&dev->mode_config.connection_mutex); > + mutex_unlock(&dev_priv->pps_mutex); > } > drm_connector_unregister(connector); > drm_connector_cleanup(connector); --=-T8O3FUUn7M6ONfHJIXEH Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJUBcD7AAoJEORIIAnNuWDF34QH/0snJmBFfkG2B8P0cZWuCxs0 yKWGenDtwkfrVrMCeuTEhT4aoTj/r7c/o8wlKimS4glMyqr/0UyTuGJrb7Sb/OWi rwBxzEuwPt3o8nlkgR6AbyV8zKdipjK2qkKisMmADQqwuQIwteDGBzyVSiE9zrAC zJUSn7G5/wrLcw7K3NWe4dLJf8vOo6ux/DozVuqXAiXXex1hYNztaBH9yz9iMoNf 8CWCU/yvXMNRVltMrOOMwBqe+w7DpxTyrIm+zGWROz9YcgiaWTt9Q7Z4CL6hchmS famI9xOMlz694fsP/C+FTMNaJo8xsWM4uJlixJ20fo/uX+uxoFDO0/8dK3rO9a8= =GIqO -----END PGP SIGNATURE----- --=-T8O3FUUn7M6ONfHJIXEH-- --===============1972834830== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============1972834830==--