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From: Imre Deak <imre.deak@intel.com>
To: ville.syrjala@linux.intel.com
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 13/14] drm/i915: Enable DP port earlier
Date: Wed, 03 Sep 2014 14:02:05 +0300	[thread overview]
Message-ID: <1409742125.15662.18.camel@intelbox> (raw)
In-Reply-To: <1408389369-22898-14-git-send-email-ville.syrjala@linux.intel.com>


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On Mon, 2014-08-18 at 22:16 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Bspec says we should enable the DP port before enabling panel power,
> and that the port must be enabled with training pattern 1. Do so.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 172 +++++++++++++++++++++++-----------------
>  1 file changed, 100 insertions(+), 72 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 28bc652..12925be 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2264,6 +2264,104 @@ static void chv_post_disable_dp(struct intel_encoder *encoder)
>  	mutex_unlock(&dev_priv->dpio_lock);
>  }
>  
> +static void
> +_intel_dp_set_link_train(struct intel_dp *intel_dp,
> +			 uint32_t *DP,
> +			 uint8_t dp_train_pat)
> +{
> +	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> +	struct drm_device *dev = intel_dig_port->base.base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	enum port port = intel_dig_port->port;
> +
> +	if (HAS_DDI(dev)) {
> +		uint32_t temp = I915_READ(DP_TP_CTL(port));
> +
> +		if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
> +			temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
> +		else
> +			temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
> +
> +		temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
> +		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
> +		case DP_TRAINING_PATTERN_DISABLE:
> +			temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
> +
> +			break;
> +		case DP_TRAINING_PATTERN_1:
> +			temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
> +			break;
> +		case DP_TRAINING_PATTERN_2:
> +			temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
> +			break;
> +		case DP_TRAINING_PATTERN_3:
> +			temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
> +			break;
> +		}
> +		I915_WRITE(DP_TP_CTL(port), temp);
> +
> +	} else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
> +		*DP &= ~DP_LINK_TRAIN_MASK_CPT;
> +
> +		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
> +		case DP_TRAINING_PATTERN_DISABLE:
> +			*DP |= DP_LINK_TRAIN_OFF_CPT;
> +			break;
> +		case DP_TRAINING_PATTERN_1:
> +			*DP |= DP_LINK_TRAIN_PAT_1_CPT;
> +			break;
> +		case DP_TRAINING_PATTERN_2:
> +			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
> +			break;
> +		case DP_TRAINING_PATTERN_3:
> +			DRM_ERROR("DP training pattern 3 not supported\n");
> +			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
> +			break;
> +		}
> +
> +	} else {
> +		if (IS_CHERRYVIEW(dev))
> +			*DP &= ~DP_LINK_TRAIN_MASK_CHV;
> +		else
> +			*DP &= ~DP_LINK_TRAIN_MASK;
> +
> +		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
> +		case DP_TRAINING_PATTERN_DISABLE:
> +			*DP |= DP_LINK_TRAIN_OFF;
> +			break;
> +		case DP_TRAINING_PATTERN_1:
> +			*DP |= DP_LINK_TRAIN_PAT_1;
> +			break;
> +		case DP_TRAINING_PATTERN_2:
> +			*DP |= DP_LINK_TRAIN_PAT_2;
> +			break;
> +		case DP_TRAINING_PATTERN_3:
> +			if (IS_CHERRYVIEW(dev)) {
> +				*DP |= DP_LINK_TRAIN_PAT_3_CHV;
> +			} else {
> +				DRM_ERROR("DP training pattern 3 not supported\n");
> +				*DP |= DP_LINK_TRAIN_PAT_2;
> +			}
> +			break;
> +		}
> +	}
> +}
> +
> +static void intel_dp_enable_port(struct intel_dp *intel_dp)
> +{
> +	struct drm_device *dev = intel_dp_to_dev(intel_dp);
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	intel_dp->DP |= DP_PORT_EN;
> +
> +	/* enable with pattern 1 (as per spec) */
> +	_intel_dp_set_link_train(intel_dp, &intel_dp->DP,
> +				 DP_TRAINING_PATTERN_1);
> +
> +	I915_WRITE(intel_dp->output_reg, intel_dp->DP);
> +	POSTING_READ(intel_dp->output_reg);
> +}
> +
>  static void intel_enable_dp(struct intel_encoder *encoder)
>  {
>  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> @@ -2274,6 +2372,7 @@ static void intel_enable_dp(struct intel_encoder *encoder)
>  	if (WARN_ON(dp_reg & DP_PORT_EN))
>  		return;
>  
> +	intel_dp_enable_port(intel_dp);
>  	intel_edp_panel_vdd_on(intel_dp);
>  	intel_edp_panel_on(intel_dp);
>  	intel_edp_panel_vdd_off(intel_dp, true);
> @@ -3174,81 +3273,10 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
>  	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_device *dev = intel_dig_port->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	enum port port = intel_dig_port->port;
>  	uint8_t buf[sizeof(intel_dp->train_set) + 1];
>  	int ret, len;
>  
> -	if (HAS_DDI(dev)) {
> -		uint32_t temp = I915_READ(DP_TP_CTL(port));
> -
> -		if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
> -			temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
> -		else
> -			temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
> -
> -		temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
> -		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
> -		case DP_TRAINING_PATTERN_DISABLE:
> -			temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
> -
> -			break;
> -		case DP_TRAINING_PATTERN_1:
> -			temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
> -			break;
> -		case DP_TRAINING_PATTERN_2:
> -			temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
> -			break;
> -		case DP_TRAINING_PATTERN_3:
> -			temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
> -			break;
> -		}
> -		I915_WRITE(DP_TP_CTL(port), temp);
> -
> -	} else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
> -		*DP &= ~DP_LINK_TRAIN_MASK_CPT;
> -
> -		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
> -		case DP_TRAINING_PATTERN_DISABLE:
> -			*DP |= DP_LINK_TRAIN_OFF_CPT;
> -			break;
> -		case DP_TRAINING_PATTERN_1:
> -			*DP |= DP_LINK_TRAIN_PAT_1_CPT;
> -			break;
> -		case DP_TRAINING_PATTERN_2:
> -			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
> -			break;
> -		case DP_TRAINING_PATTERN_3:
> -			DRM_ERROR("DP training pattern 3 not supported\n");
> -			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
> -			break;
> -		}
> -
> -	} else {
> -		if (IS_CHERRYVIEW(dev))
> -			*DP &= ~DP_LINK_TRAIN_MASK_CHV;
> -		else
> -			*DP &= ~DP_LINK_TRAIN_MASK;
> -
> -		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
> -		case DP_TRAINING_PATTERN_DISABLE:
> -			*DP |= DP_LINK_TRAIN_OFF;
> -			break;
> -		case DP_TRAINING_PATTERN_1:
> -			*DP |= DP_LINK_TRAIN_PAT_1;
> -			break;
> -		case DP_TRAINING_PATTERN_2:
> -			*DP |= DP_LINK_TRAIN_PAT_2;
> -			break;
> -		case DP_TRAINING_PATTERN_3:
> -			if (IS_CHERRYVIEW(dev)) {
> -				*DP |= DP_LINK_TRAIN_PAT_3_CHV;
> -			} else {
> -				DRM_ERROR("DP training pattern 3 not supported\n");
> -				*DP |= DP_LINK_TRAIN_PAT_2;
> -			}
> -			break;
> -		}
> -	}
> +	_intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
>  
>  	I915_WRITE(intel_dp->output_reg, *DP);
>  	POSTING_READ(intel_dp->output_reg);


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_______________________________________________
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  reply	other threads:[~2014-09-03 11:02 UTC|newest]

Thread overview: 63+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-08-18 19:15 [PATCH 00/14] drm/i915: edp vdd locking and prep for power sequencer kick ville.syrjala
2014-08-18 19:15 ` [PATCH 01/14] drm/i915: Parametrize PANEL_PORT_SELECT_VLV ville.syrjala
2014-08-19  6:58   ` Jani Nikula
2014-08-18 19:15 ` [PATCH 02/14] drm/i915: Reorganize vlv eDP reboot notifier ville.syrjala
2014-08-18 21:28   ` Clint Taylor
2014-08-19  7:00   ` Jani Nikula
2014-08-26 12:58     ` Ville Syrjälä
2014-08-26 13:21       ` Jani Nikula
2014-08-26 13:30         ` Ville Syrjälä
2014-08-26 13:36         ` Daniel Vetter
2014-08-26 14:06           ` Ville Syrjälä
2014-09-04 17:47             ` Clint Taylor
2014-09-05  8:23               ` Ville Syrjälä
2014-08-18 19:15 ` [PATCH 03/14] drm/i915: Use intel_edp_panel_vdd_on() in intel_dp_probe_mst() ville.syrjala
2014-08-19  7:12   ` Jani Nikula
2014-08-18 19:15 ` [PATCH 04/14] drm/i915: Rename edp vdd funcs for consistency ville.syrjala
2014-08-19  7:20   ` Jani Nikula
2014-08-19 10:24     ` [PATCH v2 " ville.syrjala
2014-08-18 19:16 ` [PATCH 05/14] drm/i915: Add a note explaining vdd on/off handling in intel_dp_aux_ch() ville.syrjala
2014-08-19  7:07   ` Jani Nikula
2014-08-18 19:16 ` [PATCH 06/14] drm/i915: Replace big nested if block with early return ville.syrjala
2014-08-19  7:24   ` Jani Nikula
2014-08-18 19:16 ` [PATCH 07/14] drm/i915: Warn about want_panel_vdd in edp_panel_vdd_off_sync() ville.syrjala
2014-08-19  7:36   ` Jani Nikula
2014-08-19 10:39     ` Ville Syrjälä
2014-08-19 13:37       ` Jani Nikula
2014-08-19 17:47         ` [PATCH 15/14] drm/i915: Add comments explaining the vdd on/off functions ville.syrjala
2014-09-03 11:52           ` Imre Deak
2014-09-04 11:55             ` [PATCH v2 " ville.syrjala
2014-09-04 13:02               ` Daniel Vetter
2014-08-26  9:21         ` [PATCH 07/14] drm/i915: Warn about want_panel_vdd in edp_panel_vdd_off_sync() Daniel Vetter
2014-08-18 19:16 ` [PATCH 08/14] drm/i915: Flatten intel_edp_panel_vdd_on() ville.syrjala
2014-08-19  7:30   ` Jani Nikula
2014-08-19 10:49     ` Ville Syrjälä
2014-08-18 19:16 ` [PATCH 09/14] drm/i915: Fix edp vdd locking ville.syrjala
2014-08-19 17:32   ` [PATCH v2 " ville.syrjala
2014-09-02 13:07     ` Imre Deak
2014-09-04 11:53       ` [PATCH v3 " ville.syrjala
2014-08-18 19:16 ` [PATCH 10/14] drm/i915: Track which port is using which pipe's power sequencer ville.syrjala
2014-08-19 17:45   ` [PATCH 10.1/14] drm/i915: Reset power sequencer pipe tracking when disp2d is off ville.syrjala
2014-08-22 14:21     ` [PATCH v2 " ville.syrjala
2014-09-02 13:47       ` Imre Deak
2014-09-04 11:54         ` [PATCH v3 " ville.syrjala
2014-09-01 11:19   ` [PATCH 10/14] drm/i915: Track which port is using which pipe's power sequencer Antti Koskipää
2014-09-04 11:54   ` [PATCH v2 " ville.syrjala
2014-08-18 19:16 ` [PATCH 11/14] drm/i915: Be more careful when picking the initial power sequencer pipe ville.syrjala
2014-09-02 13:52   ` Imre Deak
2014-09-04 12:59   ` Daniel Vetter
2014-08-18 19:16 ` [PATCH 12/14] drm/i915: Turn on panel power before doing aux transfers ville.syrjala
2014-08-19  7:33   ` Jani Nikula
2014-08-19 10:57     ` Ville Syrjälä
2014-08-26 12:41       ` Daniel Vetter
2014-09-02 14:02   ` Imre Deak
2014-08-18 19:16 ` [PATCH 13/14] drm/i915: Enable DP port earlier ville.syrjala
2014-09-03 11:02   ` Imre Deak [this message]
2014-08-18 19:16 ` [PATCH 14/14] drm/i915: Move DP port disable to post_disable for pch platforms ville.syrjala
2014-08-26  9:43   ` Daniel Vetter
2014-09-03 11:20   ` Imre Deak
2014-08-19  7:45 ` [PATCH 00/14] drm/i915: edp vdd locking and prep for power sequencer kick Jani Nikula
2014-08-26  9:37   ` Daniel Vetter
2014-08-19  8:08 ` Jani Nikula
2014-08-19 10:46   ` Ville Syrjälä
2014-08-26  9:35     ` Daniel Vetter

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