From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 13/14] drm/i915: Enable DP port earlier Date: Wed, 03 Sep 2014 14:02:05 +0300 Message-ID: <1409742125.15662.18.camel@intelbox> References: <1408389369-22898-1-git-send-email-ville.syrjala@linux.intel.com> <1408389369-22898-14-git-send-email-ville.syrjala@linux.intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0299213119==" Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 107976E520 for ; Wed, 3 Sep 2014 04:02:43 -0700 (PDT) In-Reply-To: <1408389369-22898-14-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0299213119== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-DMH14NLPGUVfGKQOHZBO" --=-DMH14NLPGUVfGKQOHZBO Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, 2014-08-18 at 22:16 +0300, ville.syrjala@linux.intel.com wrote: > From: Ville Syrj=C3=A4l=C3=A4 >=20 > Bspec says we should enable the DP port before enabling panel power, > and that the port must be enabled with training pattern 1. Do so. >=20 > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 Reviewed-by: Imre Deak > --- > drivers/gpu/drm/i915/intel_dp.c | 172 +++++++++++++++++++++++-----------= ------ > 1 file changed, 100 insertions(+), 72 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel= _dp.c > index 28bc652..12925be 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -2264,6 +2264,104 @@ static void chv_post_disable_dp(struct intel_enco= der *encoder) > mutex_unlock(&dev_priv->dpio_lock); > } > =20 > +static void > +_intel_dp_set_link_train(struct intel_dp *intel_dp, > + uint32_t *DP, > + uint8_t dp_train_pat) > +{ > + struct intel_digital_port *intel_dig_port =3D dp_to_dig_port(intel_dp); > + struct drm_device *dev =3D intel_dig_port->base.base.dev; > + struct drm_i915_private *dev_priv =3D dev->dev_private; > + enum port port =3D intel_dig_port->port; > + > + if (HAS_DDI(dev)) { > + uint32_t temp =3D I915_READ(DP_TP_CTL(port)); > + > + if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) > + temp |=3D DP_TP_CTL_SCRAMBLE_DISABLE; > + else > + temp &=3D ~DP_TP_CTL_SCRAMBLE_DISABLE; > + > + temp &=3D ~DP_TP_CTL_LINK_TRAIN_MASK; > + switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { > + case DP_TRAINING_PATTERN_DISABLE: > + temp |=3D DP_TP_CTL_LINK_TRAIN_NORMAL; > + > + break; > + case DP_TRAINING_PATTERN_1: > + temp |=3D DP_TP_CTL_LINK_TRAIN_PAT1; > + break; > + case DP_TRAINING_PATTERN_2: > + temp |=3D DP_TP_CTL_LINK_TRAIN_PAT2; > + break; > + case DP_TRAINING_PATTERN_3: > + temp |=3D DP_TP_CTL_LINK_TRAIN_PAT3; > + break; > + } > + I915_WRITE(DP_TP_CTL(port), temp); > + > + } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port !=3D PORT_A)) { > + *DP &=3D ~DP_LINK_TRAIN_MASK_CPT; > + > + switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { > + case DP_TRAINING_PATTERN_DISABLE: > + *DP |=3D DP_LINK_TRAIN_OFF_CPT; > + break; > + case DP_TRAINING_PATTERN_1: > + *DP |=3D DP_LINK_TRAIN_PAT_1_CPT; > + break; > + case DP_TRAINING_PATTERN_2: > + *DP |=3D DP_LINK_TRAIN_PAT_2_CPT; > + break; > + case DP_TRAINING_PATTERN_3: > + DRM_ERROR("DP training pattern 3 not supported\n"); > + *DP |=3D DP_LINK_TRAIN_PAT_2_CPT; > + break; > + } > + > + } else { > + if (IS_CHERRYVIEW(dev)) > + *DP &=3D ~DP_LINK_TRAIN_MASK_CHV; > + else > + *DP &=3D ~DP_LINK_TRAIN_MASK; > + > + switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { > + case DP_TRAINING_PATTERN_DISABLE: > + *DP |=3D DP_LINK_TRAIN_OFF; > + break; > + case DP_TRAINING_PATTERN_1: > + *DP |=3D DP_LINK_TRAIN_PAT_1; > + break; > + case DP_TRAINING_PATTERN_2: > + *DP |=3D DP_LINK_TRAIN_PAT_2; > + break; > + case DP_TRAINING_PATTERN_3: > + if (IS_CHERRYVIEW(dev)) { > + *DP |=3D DP_LINK_TRAIN_PAT_3_CHV; > + } else { > + DRM_ERROR("DP training pattern 3 not supported\n"); > + *DP |=3D DP_LINK_TRAIN_PAT_2; > + } > + break; > + } > + } > +} > + > +static void intel_dp_enable_port(struct intel_dp *intel_dp) > +{ > + struct drm_device *dev =3D intel_dp_to_dev(intel_dp); > + struct drm_i915_private *dev_priv =3D dev->dev_private; > + > + intel_dp->DP |=3D DP_PORT_EN; > + > + /* enable with pattern 1 (as per spec) */ > + _intel_dp_set_link_train(intel_dp, &intel_dp->DP, > + DP_TRAINING_PATTERN_1); > + > + I915_WRITE(intel_dp->output_reg, intel_dp->DP); > + POSTING_READ(intel_dp->output_reg); > +} > + > static void intel_enable_dp(struct intel_encoder *encoder) > { > struct intel_dp *intel_dp =3D enc_to_intel_dp(&encoder->base); > @@ -2274,6 +2372,7 @@ static void intel_enable_dp(struct intel_encoder *e= ncoder) > if (WARN_ON(dp_reg & DP_PORT_EN)) > return; > =20 > + intel_dp_enable_port(intel_dp); > intel_edp_panel_vdd_on(intel_dp); > intel_edp_panel_on(intel_dp); > intel_edp_panel_vdd_off(intel_dp, true); > @@ -3174,81 +3273,10 @@ intel_dp_set_link_train(struct intel_dp *intel_dp= , > struct intel_digital_port *intel_dig_port =3D dp_to_dig_port(intel_dp); > struct drm_device *dev =3D intel_dig_port->base.base.dev; > struct drm_i915_private *dev_priv =3D dev->dev_private; > - enum port port =3D intel_dig_port->port; > uint8_t buf[sizeof(intel_dp->train_set) + 1]; > int ret, len; > =20 > - if (HAS_DDI(dev)) { > - uint32_t temp =3D I915_READ(DP_TP_CTL(port)); > - > - if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) > - temp |=3D DP_TP_CTL_SCRAMBLE_DISABLE; > - else > - temp &=3D ~DP_TP_CTL_SCRAMBLE_DISABLE; > - > - temp &=3D ~DP_TP_CTL_LINK_TRAIN_MASK; > - switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { > - case DP_TRAINING_PATTERN_DISABLE: > - temp |=3D DP_TP_CTL_LINK_TRAIN_NORMAL; > - > - break; > - case DP_TRAINING_PATTERN_1: > - temp |=3D DP_TP_CTL_LINK_TRAIN_PAT1; > - break; > - case DP_TRAINING_PATTERN_2: > - temp |=3D DP_TP_CTL_LINK_TRAIN_PAT2; > - break; > - case DP_TRAINING_PATTERN_3: > - temp |=3D DP_TP_CTL_LINK_TRAIN_PAT3; > - break; > - } > - I915_WRITE(DP_TP_CTL(port), temp); > - > - } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port !=3D PORT_A)) { > - *DP &=3D ~DP_LINK_TRAIN_MASK_CPT; > - > - switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { > - case DP_TRAINING_PATTERN_DISABLE: > - *DP |=3D DP_LINK_TRAIN_OFF_CPT; > - break; > - case DP_TRAINING_PATTERN_1: > - *DP |=3D DP_LINK_TRAIN_PAT_1_CPT; > - break; > - case DP_TRAINING_PATTERN_2: > - *DP |=3D DP_LINK_TRAIN_PAT_2_CPT; > - break; > - case DP_TRAINING_PATTERN_3: > - DRM_ERROR("DP training pattern 3 not supported\n"); > - *DP |=3D DP_LINK_TRAIN_PAT_2_CPT; > - break; > - } > - > - } else { > - if (IS_CHERRYVIEW(dev)) > - *DP &=3D ~DP_LINK_TRAIN_MASK_CHV; > - else > - *DP &=3D ~DP_LINK_TRAIN_MASK; > - > - switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { > - case DP_TRAINING_PATTERN_DISABLE: > - *DP |=3D DP_LINK_TRAIN_OFF; > - break; > - case DP_TRAINING_PATTERN_1: > - *DP |=3D DP_LINK_TRAIN_PAT_1; > - break; > - case DP_TRAINING_PATTERN_2: > - *DP |=3D DP_LINK_TRAIN_PAT_2; > - break; > - case DP_TRAINING_PATTERN_3: > - if (IS_CHERRYVIEW(dev)) { > - *DP |=3D DP_LINK_TRAIN_PAT_3_CHV; > - } else { > - DRM_ERROR("DP training pattern 3 not supported\n"); > - *DP |=3D DP_LINK_TRAIN_PAT_2; > - } > - break; > - } > - } > + _intel_dp_set_link_train(intel_dp, DP, dp_train_pat); > =20 > I915_WRITE(intel_dp->output_reg, *DP); > POSTING_READ(intel_dp->output_reg); --=-DMH14NLPGUVfGKQOHZBO Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJUBvUtAAoJEORIIAnNuWDFSQgIAN6cO8C82t4WRD10GU2FwjfV hpYq5WTHsLIbBTzW51QwgTDn1CpooZLEt96yA00bl0c6TjIVMUMUTaj8vup2vcw/ MB7mC1m1aTC+iz8CumYe7QPUTvwIM3mu2KkpTldHA+GCkwkqq95VTHpVMWYf70KH QTnMCt4S/5aHZ7lDMegUS/aLPfK9CdPwLhUMukyWD7E1TkasNE+MBAMmtMj3LfEG 5bqYvyU0LmKpwEKixIdlBXQ2mZv/cphXI3qFFX+OO96L5EIBeGddVb/ly6bM9Hsm fY7kflAcyU/yOkvkhOqPkkcZpwM1Tl0Xl18a8I7lVJZufabvpAIwNBhxA3XKM64= =FCR+ -----END PGP SIGNATURE----- --=-DMH14NLPGUVfGKQOHZBO-- --===============0299213119== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0299213119==--