From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 70/89] drm/i915/skl: Register definition for SKL power well Date: Tue, 16 Sep 2014 15:43:41 +0300 Message-ID: <1410871421.19704.8.camel@intelbox> References: <1409830075-11139-1-git-send-email-damien.lespiau@intel.com> <1409830075-11139-71-git-send-email-damien.lespiau@intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1296449679==" Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 097856E0A3 for ; Tue, 16 Sep 2014 05:44:06 -0700 (PDT) In-Reply-To: <1409830075-11139-71-git-send-email-damien.lespiau@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Damien Lespiau Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============1296449679== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-F5XYMfNHD8vfnc4ZIgib" --=-F5XYMfNHD8vfnc4ZIgib Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, 2014-09-04 at 12:27 +0100, Damien Lespiau wrote: > From: Satheeshakrishna M >=20 > Defining new bit fields for SKL display power wells. >=20 > v2: Clean up unused macros >=20 > Signed-off-by: Satheeshakrishna M > Signed-off-by: Damien Lespiau This looks ok, but it should be squashed into 71/89, where it's first used. Either way: Reviewed-by: Imre Deak > --- > drivers/gpu/drm/i915/i915_reg.h | 7 +++++++ > 1 file changed, 7 insertions(+) >=20 > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index 794d0ba..4d072a8 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6133,6 +6133,13 @@ enum punit_power_well { > #define HSW_PWR_WELL_FORCE_ON (1<<19) > #define HSW_PWR_WELL_CTL6 0x45414 > =20 > +/* SKL Fuse Status */ > +#define SKL_FUSE_STATUS 0x42000 > +#define SKL_FUSE_DOWNLOAD_STATUS (1<<31) > +#define SKL_FUSE_PG0_DIST_STATUS (1<<27) > +#define SKL_FUSE_PG1_DIST_STATUS (1<<26) > +#define SKL_FUSE_PG2_DIST_STATUS (1<<25) > + > /* Per-pipe DDI Function Control */ > #define TRANS_DDI_FUNC_CTL_A 0x60400 > #define TRANS_DDI_FUNC_CTL_B 0x61400 --=-F5XYMfNHD8vfnc4ZIgib Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJUGDB9AAoJEORIIAnNuWDFjQQH/jirkZ7uyA5T4+AJyG8nHePq 12a2AdphlOUBioNNi7nfumH08hywFApLVPhuhC9mU6xLRxWcR3c/2IYqDzpK/PmP Z8UfeRId3XgN3duJ8S8A7HL4htuqOlizlC1y+0wqjNEhU35a75Ew+Eiza7foZI9s pfowjHRE/KkYntHmN2kBK1W3XnS7XcUQIJ4dT2u7/VRXr+V5JYk/nkYDvFjEdw4I fc1hfqJblbeYLeRDToW0KQvj2daPVAzU4yY0R8O/P/F2GVa0pWtz5TR4eXSjd+GV Epj0pf7gGLqXXQC7jLK+JWlJoK+rUJEoTSfhoAfcqMwDEwTD5J4rwDlxFzDRFYE= =pvgY -----END PGP SIGNATURE----- --=-F5XYMfNHD8vfnc4ZIgib-- --===============1296449679== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============1296449679==--