From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 73/89] drm/i915/skl: Enabling MISC IO power well Date: Tue, 16 Sep 2014 17:12:06 +0300 Message-ID: <1410876726.19704.52.camel@intelbox> References: <1409830075-11139-1-git-send-email-damien.lespiau@intel.com> <1409830075-11139-74-git-send-email-damien.lespiau@intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0609169703==" Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id A4C286E453 for ; Tue, 16 Sep 2014 07:12:42 -0700 (PDT) In-Reply-To: <1409830075-11139-74-git-send-email-damien.lespiau@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Damien Lespiau Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0609169703== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-66P01nq8wJcvyc8NtNZo" --=-66P01nq8wJcvyc8NtNZo Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, 2014-09-04 at 12:27 +0100, Damien Lespiau wrote: > From: Satheeshakrishna M >=20 > Earlier it was thought that MISC IO is always ON power well. > But it doesn't looks like the case as confirmed by the HW team. > Adding code to enable/disable MISC IO power well. >=20 > v2: Use power well data for comparison (Imre) >=20 > Signed-off-by: Satheeshakrishna M > Signed-off-by: Damien Lespiau > --- > drivers/gpu/drm/i915/intel_pm.c | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) >=20 > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 853b596..5425d85 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -7204,6 +7204,21 @@ static void hsw_set_power_well(struct drm_i915_pri= vate *dev_priv, > BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ > BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ > BIT(POWER_DOMAIN_INIT)) > +#define SKL_DISPLAY_MISC_IO_POWER_DOMAINS ( \ > + BIT(POWER_DOMAIN_AUX_A) | \ > + BIT(POWER_DOMAIN_AUX_B) | \ > + BIT(POWER_DOMAIN_AUX_C) | \ > + BIT(POWER_DOMAIN_AUX_D) | \ > + BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ > + BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ > + BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ > + BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ > + BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ > + BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ > + BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ > + BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ > + BIT(POWER_DOMAIN_AUDIO) | \ > + BIT(POWER_DOMAIN_INIT)) =46rom the bspec page "Skylake Sequences to Initialize Display": """ Most display engine functions will not operate while display is not initialized. Only basic PCI, I/O, and MMIO register read/write operations are supported when display is not initialized. """ And for the display to be initialized we need power well#1 and the misc power well. Based on this we need the misc power well (and power well#1) for all domains, so simply: #define SKL_DISPLAY_MISC_IO_POWER_DOMAINS POWER_DOMAIN_MASK > #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ > (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ > SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ > @@ -7241,6 +7256,7 @@ static void skl_set_power_well(struct drm_i915_priv= ate *dev_priv, > case SKL_DISP_PW_DDI_B: > case SKL_DISP_PW_DDI_C: > case SKL_DISP_PW_DDI_D: > + case SKL_DISP_PW_MISC_IO: > break; > default: > return; > @@ -8211,6 +8227,12 @@ static struct i915_power_well skl_power_wells[] = =3D { > .ops =3D &skl_power_well_ops, > .data =3D SKL_DISP_PW_DDI_D, > }, > + { > + .name =3D "MISC IO power well", > + .domains =3D SKL_DISPLAY_MISC_IO_POWER_DOMAINS, > + .ops =3D &skl_power_well_ops, > + .data =3D SKL_DISP_PW_MISC_IO, > + } Based on the above bspec page, the misc power well needs to be enabled before any other power wells, so it needs to be the first entry. Optionally this patch could be squashed into 71/89. With the above changes: Reviewed-by: Imre Deak > }; > =20 > #define set_power_wells(power_domains, __power_wells) ({ \ --=-66P01nq8wJcvyc8NtNZo Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJUGEU2AAoJEORIIAnNuWDFQ3IIAJ8FKuDTg/0M/NiqZKX+FpLv KLgvQs8Af+98pV1K9fjvHkL+DtVTZWGNtDFmIE55bbFNOyT6oNrzyhiDX168xuO7 jkVETuVG1jWPKTT07rWHJdqO5O9Lm1c6PbSnaxY0rtOKf0nYXFYGAarH4p0Xo0VJ hRffy/Xh5gcLsyztR69NlUn1o5Wx9oz+PbIseQlcZa4SztAvsYXVFAOi5p88eOEi JkQLMEEks4/hrzpGyl4YnfrMoNcrtU5B5rtsOf5EU9FSX8Sg36D3xwUVpTJhJ4+B +p7nWE5LHWMCzVl+MQjAtubRVT8GkDpIzj9uUe51C0qVf05cVKFpT5y0pul2yJ8= =AHuE -----END PGP SIGNATURE----- --=-66P01nq8wJcvyc8NtNZo-- --===============0609169703== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0609169703==--