From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rodrigo Vivi Subject: [PATCH 4/4] drm/i915: Make sure PSR is ready for been re-enabled. Date: Tue, 16 Sep 2014 19:19:08 -0400 Message-ID: <1410909548-4945-4-git-send-email-rodrigo.vivi@intel.com> References: <1410909548-4945-1-git-send-email-rodrigo.vivi@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-pa0-f52.google.com (mail-pa0-f52.google.com [209.85.220.52]) by gabe.freedesktop.org (Postfix) with ESMTP id 1FEFC6E301 for ; Tue, 16 Sep 2014 16:19:19 -0700 (PDT) Received: by mail-pa0-f52.google.com with SMTP id kq14so760723pab.11 for ; Tue, 16 Sep 2014 16:19:19 -0700 (PDT) In-Reply-To: <1410909548-4945-1-git-send-email-rodrigo.vivi@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org Cc: Rodrigo Vivi List-Id: intel-gfx@lists.freedesktop.org Let's make sure PSR is propperly disabled before to re-enabled it. According to Spec, after disabled PSR CTL, the Idle state might occur up to 24ms, that is one full frame time (1/refresh rate), plus SRD exit training time (max of 6ms), plus SRD aux channel handshake (max of 1.5ms). So if something went wrong PSR will be disabled until next full enable/disable setup. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_dp.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 2f0eee5..658a911 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1885,6 +1885,17 @@ static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) WARN_ON(dev_priv->psr.active); lockdep_assert_held(&dev_priv->psr.lock); + /* We have to make sure PSR is ready for re-enable + * otherwise it keeps disabled until next full enable/disable cycle. + * PSR might take up to 24 ms to get fully disabled + * and be ready for re-enable. + */ + if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & + EDP_PSR_STATUS_STATE_MASK) == 0, 24)) { + DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); + return; + } + /* Enable/Re-enable PSR on the host */ intel_edp_psr_enable_source(intel_dp); -- 1.9.3