[PATCH 0/4] [RFC] Stage shared dpll configs

[Ander Conselvan de Oliveira <conselvan2@gmail.com>]

From: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>

Hi,

This series changes the mode set sequence so that the clock and PLL
logic that was done in the *_crtc_mode_set() hooks is done before
disabling crtcs. This avoids having to restore the old configuration
in the case of failure, since the hardware was never touched.

The changes went through only light testing in a single platform. But I'd
like to get comments on the general approach sooner rather than later,
hence this RFC.

Thanks,
Ander

Ander Conselvan de Oliveira (4):
  drm/i915: Replace some loop through encoders with
    intel_pipe_has_type()
  drm/i915: Make *_crtc_mode_set work on new_config
  drm/i915: Convert shared dpll reference count to a crtc mask
  drm/i915: Compute clocks and choose DPLLs before disabling crtcs

 drivers/gpu/drm/i915/i915_debugfs.c  |   4 +-
 drivers/gpu/drm/i915/i915_drv.h      |  11 +-
 drivers/gpu/drm/i915/intel_ddi.c     |   6 +-
 drivers/gpu/drm/i915/intel_display.c | 346 ++++++++++++++++++++++-------------
 4 files changed, 230 insertions(+), 137 deletions(-)

-- 
1.8.3.2