From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yu Zhang Subject: [PATCH v2 3/8] drm/i915: Partition the fence registers for vgpu in i915 driver Date: Fri, 17 Oct 2014 13:37:14 +0800 Message-ID: <1413524239-8614-4-git-send-email-yu.c.zhang@linux.intel.com> References: <1413524239-8614-1-git-send-email-yu.c.zhang@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 7DFF26E301 for ; Thu, 16 Oct 2014 23:05:34 -0700 (PDT) In-Reply-To: <1413524239-8614-1-git-send-email-yu.c.zhang@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org In XenGT, the fence registers are partitioned by multiple vgpu instances in different VMs. Routine i915_gem_load() is modified to reset the num_fence_regs, when the driver detects it's runing in a VM. And the allocated fence numbers is provided in PV INFO page structure. Signed-off-by: Yu Zhang Signed-off-by: Jike Song Signed-off-by: Eddie Dong --- drivers/gpu/drm/i915/i915_gem.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index e9c783d..a0eec59 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -28,6 +28,7 @@ #include #include #include +#include "i915_vgt_if.h" #include "i915_drv.h" #include "i915_trace.h" #include "intel_drv.h" @@ -4988,6 +4989,10 @@ i915_gem_load(struct drm_device *dev) else dev_priv->num_fence_regs = 8; + if (intel_vgpu_active(dev)) + dev_priv->num_fence_regs = + I915_READ(vgtif_reg(avail_rs.fence_num)); + /* Initialize fence registers to zero */ INIT_LIST_HEAD(&dev_priv->mm.fence_list); i915_gem_restore_fences(dev); -- 1.9.1