From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yu Zhang Subject: [PATCH v2 7/8] drm/i915: Create vgpu specific write MMIO to reduce traps Date: Fri, 17 Oct 2014 13:37:18 +0800 Message-ID: <1413524239-8614-8-git-send-email-yu.c.zhang@linux.intel.com> References: <1413524239-8614-1-git-send-email-yu.c.zhang@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 022376E2FA for ; Thu, 16 Oct 2014 23:06:05 -0700 (PDT) In-Reply-To: <1413524239-8614-1-git-send-email-yu.c.zhang@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org In the virtualized environment, forcewake operations are not necessory for the driver, because mmio accesses will be trapped and emulated by the host side, and real forcewake operations are also done in the host. New mmio write handlers are added to directly call the __raw_i915_write, therefore will reduce many traps and increase the overall performance for drivers runing in the VM with Intel GVT-g enhancement. v2: take Chris' comments: - register the mmio hooks in intel_uncore_init() Signed-off-by: Yu Zhang Signed-off-by: Jike Song Signed-off-by: Kevin Tian --- drivers/gpu/drm/i915/intel_uncore.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index d5f39f3..ec6d5ce 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -719,6 +719,14 @@ hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) REG_WRITE_FOOTER; \ } +#define __vgpu_write(x) \ +static void \ +vgpu_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ + REG_WRITE_HEADER; \ + __raw_i915_write##x(dev_priv, reg, val); \ + REG_WRITE_FOOTER; \ +} + static const u32 gen8_shadowed_regs[] = { FORCEWAKE_MT, GEN6_RPNSWREQ, @@ -813,6 +821,10 @@ __gen4_write(8) __gen4_write(16) __gen4_write(32) __gen4_write(64) +__vgpu_write(8) +__vgpu_write(16) +__vgpu_write(32) +__vgpu_write(64) #undef __chv_write #undef __gen8_write @@ -820,6 +832,7 @@ __gen4_write(64) #undef __gen6_write #undef __gen5_write #undef __gen4_write +#undef __vgpu_write #undef REG_WRITE_FOOTER #undef REG_WRITE_HEADER @@ -950,6 +963,13 @@ void intel_uncore_init(struct drm_device *dev) dev_priv->uncore.funcs.mmio_readq = gen4_read64; break; } + + if (intel_vgpu_active(dev)) { + dev_priv->uncore.funcs.mmio_writeb = vgpu_write8; + dev_priv->uncore.funcs.mmio_writew = vgpu_write16; + dev_priv->uncore.funcs.mmio_writel = vgpu_write32; + dev_priv->uncore.funcs.mmio_writeq = vgpu_write64; + } } void intel_uncore_fini(struct drm_device *dev) -- 1.9.1