Re: [PATCH 51/89] drm/i915/gen9: Add 2us read latency to WM level

Ville Syrjälä
2014-09-19T10:04:10Z

On Thu, Sep 04, 2014 at 12:27:17PM +0100, Damien Lespiau wrote:
> From: Vandana Kannan <vandana.kannan@intel.com>
>
> According to the updated Bspec, The mailbox response data is not currently
> accounting for memory read latency. Add 2 microseconds to the result for
> each level.
> This patch adds 2us to latency of level 0 for all cases and
> for all other levels (1-7) only if latency[level] > 0.
>
> v2: Slightly rework the patch and add a big comment (Damien)
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v1)
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> Reviewed-by: M, Satheeshakrishna <satheeshakrishna.m@intel.com> (v1)
> Cc: Lespiau, Damien <damien.lespiau@intel.com>
> Cc: M, Satheeshakrishna <satheeshakrishna.m@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
> drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1e56067..16ad008 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2254,6 +2254,7 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
> if (IS_GEN9(dev)) {
> uint32_t val;
> int ret;
> + int level, max_level = ilk_wm_max_level(dev);
>
> /* read the first set of memory latencies[0:3] */
> val = 0; /* data0 to be programmed to 0 for first set */
> @@ -2267,6 +2268,7 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
> DRM_ERROR("SKL Mailbox read error = %d\n", ret);
> return;
> }
> +
> wm[0] = val & GEN9_MEM_LAT_LEVEL_MASK;
> wm[1] = (val >> GEN9_MEM_LAT_LEVEL_1_5_SHIFT) &
> GEN9_MEM_LAT_LEVEL_MASK;
> @@ -2293,6 +2295,22 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
> GEN9_MEM_LAT_LEVEL_MASK;
> wm[7] = (val >> GEN9_MEM_LAT_LEVEL_3_7_SHIFT) &
> GEN9_MEM_LAT_LEVEL_MASK;
> +
> + /*
> + * punit doesn't take into account the read latency so we need
> + * to add 2us to the various latency levels we retrieve from
> + * the punit.
> + * - W0 is a bit special in that it's the only level that
> + * can't be disabled if we want to have display working, so
> + * we always add 2us there.
> + * - For levels >=1, punit returns 0us latency when they are
> + * disabled, so we respect that and don't add 2us then
> + */
> + wm[0] += 2;
> + for (level = 1; level <= max_level; level++)
> + if (wm[level] != 0)
> + wm[level] += 2;
> +
> } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> uint64_t sskpd = I915_READ64(MCH_SSKPD);
>
> --
> 1.8.3.1
>
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--
Ville Syrjälä
Intel OTC