Re: [PATCH 70/89] drm/i915/skl: Register definition for SKL power well

Imre Deak
2014-09-16T12:44:06Z

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On Thu, 2014-09-04 at 12:27 +0100, Damien Lespiau wrote:
> From: Satheeshakrishna M <satheeshakrishna.m@intel.com>
>
> Defining new bit fields for SKL display power wells.
>
> v2: Clean up unused macros
>
> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

This looks ok, but it should be squashed into 71/89, where it's first
used. Either way:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
> drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 794d0ba..4d072a8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6133,6 +6133,13 @@ enum punit_power_well {
> #define HSW_PWR_WELL_FORCE_ON (1<<19)
> #define HSW_PWR_WELL_CTL6 0x45414
>
> +/* SKL Fuse Status */
> +#define SKL_FUSE_STATUS 0x42000
> +#define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
> +#define SKL_FUSE_PG0_DIST_STATUS (1<<27)
> +#define SKL_FUSE_PG1_DIST_STATUS (1<<26)
> +#define SKL_FUSE_PG2_DIST_STATUS (1<<25)
> +
> /* Per-pipe DDI Function Control */
> #define TRANS_DDI_FUNC_CTL_A 0x60400
> #define TRANS_DDI_FUNC_CTL_B 0x61400

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