[PATCH 52/89] drm/i915/gen9: Disable WM if corresponding latency is 0

Damien Lespiau
2014-09-04T11:28:46Z

From: Vandana Kannan <vandana.kannan@intel.com>

According to updated BSpec, If level 1 or any higher level has a value of 0x00,
that level and any higher levels are unused and the associated watermark
registers must not be enabled.

This patch checks for latency 0 for level >=1 and does not enable WM
corresponding to level m | m>=n, if level n (n != 0) has a 0us latency.

v2: Satheesh's review comments
- zero-out latency values (for all higher levels if latency of given
level is zero ) in read_wm_latency() function itself

v3: removed redundant check as per Satheesh's observation.
v4: rebase on top before merging (Damien)

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Reviewed-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v3)
Cc: Satheeshakrishna M <satheeshakrishna.m@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 16ad008..fdf297f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2253,7 +2253,7 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])

if (IS_GEN9(dev)) {
uint32_t val;
- int ret;
+ int ret, i;
int level, max_level = ilk_wm_max_level(dev);

/* read the first set of memory latencies[0:3] */
@@ -2305,12 +2305,22 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
* we always add 2us there.
* - For levels >=1, punit returns 0us latency when they are
* disabled, so we respect that and don't add 2us then
+ *
+ * Additionally, if a level n (n > 1) has a 0us latency, all
+ * levels m (m >= n) need to be disabled. We make sure to
+ * sanitize the values out of the punit to satisfy this
+ * requirement.
*/
wm[0] += 2;
for (level = 1; level <= max_level; level++)
if (wm[level] != 0)
wm[level] += 2;
+ else {
+ for (i = level + 1; i <= max_level; i++)
+ wm[i] = 0;

+ break;
+ }
} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
uint64_t sskpd = I915_READ64(MCH_SSKPD);

@@ -3253,7 +3263,7 @@ static bool skl_compute_plane_wm(struct skl_pipe_wm_parameters *p,
uint32_t method1, method2, plane_bytes_per_line;
uint32_t result_bytes;

- if (!p->active || !p_params->enabled) {
+ if (mem_value == 0 || !p->active || !p_params->enabled) {
*res_blocks = PLANE_WM_BLOCKS_DEFAULT;
*res_lines = PLANE_WM_LINES_DEFAULT;
return false;
--
1.8.3.1