Re: [PATCH 59/89] drm/i915/skl: Structure/enum definitions for SKL clocks

Paulo Zanoni
2014-09-22T18:25:31Z

2014-09-04 8:27 GMT-03:00 Damien Lespiau <damien.lespiau@intel.com>:
> From: Satheeshakrishna M <satheeshakrishna.m@intel.com>
>
> Adding structure/enum for SKL clocking implementation.
>
> v2: Addressed Damien's comment
> - Removed internal structure from this header file
>
> v3: Stove this into the generic intel_dpll_id enum and give them the established
> DPLL_ID_ prefixes. (Daniel)
>
> v4: - We'll only try to share DPLL1/2/3, leaving DPLL0 to eDP
> - Use SKL in the skylake shared DPLL names
> - Re-add the skl_dpll enum
> (Damien)
>
> v5: Remove SKL_DPLL_NONE (Daniel)
>
> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v2)
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v4,v5)
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v3)

The changes contained on this patch should be part of another patch. I
can't really review this if I don't know how those things, especially
enum skl_dpll are going to be used. And it also makes the lives of
backporters harder.

Also, I guess that a patch with 3 signed-off-by stamps shouldn't
really need an additional reviewed-by stamp, right? So maybe this
should just be merged.

> ---
> drivers/gpu/drm/i915/i915_drv.h | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 84defa4..65e5ffb 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -206,10 +206,15 @@ enum intel_dpll_id {
> /* real shared dpll ids must be >= 0 */
> DPLL_ID_PCH_PLL_A = 0,
> DPLL_ID_PCH_PLL_B = 1,
> + /* hsw/bdw */
> DPLL_ID_WRPLL1 = 0,
> DPLL_ID_WRPLL2 = 1,
> + /* skl */
> + DPLL_ID_SKL_DPLL1 = 0,
> + DPLL_ID_SKL_DPLL2 = 1,
> + DPLL_ID_SKL_DPLL3 = 2,
> };
> -#define I915_NUM_PLLS 2
> +#define I915_NUM_PLLS 3
>
> struct intel_dpll_hw_state {
> /* i9xx, pch plls */
> @@ -243,6 +248,13 @@ struct intel_shared_dpll {
> struct intel_dpll_hw_state *hw_state);
> };
>
> +enum skl_dpll {
> + SKL_DPLL0,
> + SKL_DPLL1,
> + SKL_DPLL2,
> + SKL_DPLL3,
> +};
> +
> /* Used by dp and fdi links */
> struct intel_link_m_n {
> uint32_t tu;
> --
> 1.8.3.1
>
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--
Paulo Zanoni