Re: [PATCH 43/89] drm/i915/skl: Read the Memory Latency Values for WM computation

Damien Lespiau
2014-09-05T08:30:30Z

On Fri, Sep 05, 2014 at 11:25:30AM +0300, Ville Syrjälä wrote:
> > +/* SKL GT Driver Mailbox registers for reading memory latencies */
> > +#define GEN9_MAILBOX_DATA1 0x13812C
> > +#define GEN9_MAILBOX_READ_MEM_LAT (0x6)
> > +#define GEN9_MAILBOX_READ_TIMEOUT 150
>
> Timeout not used anywhere. Also spec says 100us.
>
> > +#define GEN9_MEM_LAT_LEVEL_MASK 0xFF
> > +#define GEN9_MEM_LAT_LEVEL_1_5_SHIFT 8
> > +#define GEN9_MEM_LAT_LEVEL_2_6_SHIFT 16
> > +#define GEN9_MEM_LAT_LEVEL_3_7_SHIFT 24
>
> This stuff should be grouped along the other pcode register defines.

Funny you mention this, I fixed those two in the v6 sent as reply
yesterday.

--
Damien