* [PATCH v1 1/2] drm/i915: Enabling RC6 immediately instead of enabling via delayed work item
@ 2014-12-01 6:58 sagar.a.kamble
2014-12-01 6:58 ` [PATCH v1 2/2] drm/i915: Deferring uncore early sanitize, sanitize, disable pc8 to resume sagar.a.kamble
0 siblings, 1 reply; 5+ messages in thread
From: sagar.a.kamble @ 2014-12-01 6:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Akash Goel, Sagar Kamble
From: Sagar Kamble <sagar.a.kamble@intel.com>
RC6 was getting enabled through deferred work item which was scheduled
after 1s. This will keep render and media well ON for 1s. Since RC6 enabling does
not involve PCU communication, processing time in intel_enable_gt_powersave will
not be increased. Enabling RC6 immediately will help power gate render and media
well immediately that will save power.
Signed-off-by: Akash Goel <akash.goel@intel.com>
Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 88 ++++++++++++++++++++++++++++-------------
1 file changed, 61 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9af0af4..1fb3084 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5276,11 +5276,11 @@ static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
valleyview_cleanup_pctx(dev);
}
-static void cherryview_enable_rps(struct drm_device *dev)
+static void cherryview_enable_rc6(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_engine_cs *ring;
- u32 gtfifodbg, val, rc6_mode = 0, pcbr;
+ u32 gtfifodbg, rc6_mode = 0, pcbr;
int i;
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
@@ -5294,10 +5294,10 @@ static void cherryview_enable_rps(struct drm_device *dev)
cherryview_check_pctx(dev_priv);
- /* 1a & 1b: Get forcewake during program sequence. Although the driver
- * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
- gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
-
+ /*
+ * Assuming RC6 disabled by uncore_sanitize we dont need to do
+ * force wake get/put here.
+ */
/* 2a: Program RC6 thresholds.*/
I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
@@ -5324,6 +5324,18 @@ static void cherryview_enable_rps(struct drm_device *dev)
rc6_mode = GEN6_RC_CTL_EI_MODE(1);
I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
+}
+
+static void cherryview_enable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 val;
+
+ WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+ /* 1a & 1b: Get forcewake during program sequence. Although the driver
+ * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
+ gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
/* 4 Program defaults and thresholds for RPS*/
I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
@@ -5367,11 +5379,11 @@ static void cherryview_enable_rps(struct drm_device *dev)
gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
}
-static void valleyview_enable_rps(struct drm_device *dev)
+static void valleyview_enable_rc6(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_engine_cs *ring;
- u32 gtfifodbg, val, rc6_mode = 0;
+ u32 gtfifodbg, rc6_mode = 0;
int i;
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
@@ -5384,25 +5396,10 @@ static void valleyview_enable_rps(struct drm_device *dev)
I915_WRITE(GTFIFODBG, gtfifodbg);
}
- /* If VLV, Forcewake all wells, else re-direct to regular path */
- gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
-
- I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
- I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
- I915_WRITE(GEN6_RP_UP_EI, 66000);
- I915_WRITE(GEN6_RP_DOWN_EI, 350000);
-
- I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
- I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
-
- I915_WRITE(GEN6_RP_CONTROL,
- GEN6_RP_MEDIA_TURBO |
- GEN6_RP_MEDIA_HW_NORMAL_MODE |
- GEN6_RP_MEDIA_IS_GFX |
- GEN6_RP_ENABLE |
- GEN6_RP_UP_BUSY_AVG |
- GEN6_RP_DOWN_IDLE_CONT);
-
+ /*
+ * Assuming RC6 disabled by uncore_sanitize we dont need to do
+ * force wake get/put here.
+ */
I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
@@ -5425,6 +5422,32 @@ static void valleyview_enable_rps(struct drm_device *dev)
intel_print_rc6_info(dev, rc6_mode);
I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
+}
+
+static void valleyview_enable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 val;
+
+ WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+ gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+
+ I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
+ I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
+ I915_WRITE(GEN6_RP_UP_EI, 66000);
+ I915_WRITE(GEN6_RP_DOWN_EI, 350000);
+
+ I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
+ I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
+
+ I915_WRITE(GEN6_RP_CONTROL,
+ GEN6_RP_MEDIA_TURBO |
+ GEN6_RP_MEDIA_HW_NORMAL_MODE |
+ GEN6_RP_MEDIA_IS_GFX |
+ GEN6_RP_ENABLE |
+ GEN6_RP_UP_BUSY_AVG |
+ GEN6_RP_DOWN_IDLE_CONT);
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
@@ -6295,6 +6318,17 @@ void intel_enable_gt_powersave(struct drm_device *dev)
mutex_unlock(&dev->struct_mutex);
} else if (INTEL_INFO(dev)->gen >= 6) {
/*
+ * Enabling RC6 for VLV & CHV here itself and only deferring turbo
+ * enabling.
+ */
+ mutex_lock(&dev_priv->rps.hw_lock);
+ if (IS_CHERRYVIEW(dev))
+ cherryview_enable_rc6(dev);
+ else if (IS_VALLEYVIEW(dev))
+ valleyview_enable_rc6(dev);
+ mutex_unlock(&dev_priv->rps.hw_lock);
+
+ /*
* PCU communication is slow and this doesn't need to be
* done at any specific time, so do this out of our fast path
* to make resume and init faster.
--
1.8.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v1 2/2] drm/i915: Deferring uncore early sanitize, sanitize, disable pc8 to resume
2014-12-01 6:58 [PATCH v1 1/2] drm/i915: Enabling RC6 immediately instead of enabling via delayed work item sagar.a.kamble
@ 2014-12-01 6:58 ` sagar.a.kamble
2014-12-01 9:16 ` Daniel Vetter
0 siblings, 1 reply; 5+ messages in thread
From: sagar.a.kamble @ 2014-12-01 6:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Akash Goel, Sagar Kamble
From: Sagar Kamble <sagar.a.kamble@intel.com>
Due to disabling of RC6 in uncore_sanitize in early resume, power is drained
till it RC6 is re-enabled post resume.
With this change RC6 disabling will be done at beginning of resume only.
This helps yield additional power benefits.
Signed-off-by: Akash Goel <akash.goel@intel.com>
Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 71be3c9..0e08ec0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -675,6 +675,13 @@ static int i915_drm_resume(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ intel_uncore_early_sanitize(dev, true);
+
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+ hsw_disable_pc8(dev_priv);
+
+ intel_uncore_sanitize(dev);
+
if (drm_core_check_feature(dev, DRIVER_MODESET)) {
mutex_lock(&dev->struct_mutex);
i915_gem_restore_gtt_mappings(dev);
@@ -761,12 +768,6 @@ static int i915_drm_resume_early(struct drm_device *dev)
if (ret)
DRM_ERROR("Resume prepare failed: %d,Continuing resume\n", ret);
- intel_uncore_early_sanitize(dev, true);
-
- if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
- hsw_disable_pc8(dev_priv);
-
- intel_uncore_sanitize(dev);
intel_power_domains_init_hw(dev_priv);
return ret;
--
1.8.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH v1 2/2] drm/i915: Deferring uncore early sanitize, sanitize, disable pc8 to resume
2014-12-01 6:58 ` [PATCH v1 2/2] drm/i915: Deferring uncore early sanitize, sanitize, disable pc8 to resume sagar.a.kamble
@ 2014-12-01 9:16 ` Daniel Vetter
2014-12-01 10:29 ` Sagar Arun Kamble
0 siblings, 1 reply; 5+ messages in thread
From: Daniel Vetter @ 2014-12-01 9:16 UTC (permalink / raw)
To: sagar.a.kamble; +Cc: intel-gfx, Akash Goel
On Mon, Dec 01, 2014 at 12:28:05PM +0530, sagar.a.kamble@intel.com wrote:
> From: Sagar Kamble <sagar.a.kamble@intel.com>
>
> Due to disabling of RC6 in uncore_sanitize in early resume, power is drained
> till it RC6 is re-enabled post resume.
> With this change RC6 disabling will be done at beginning of resume only.
> This helps yield additional power benefits.
>
> Signed-off-by: Akash Goel <akash.goel@intel.com>
> Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
A bit of git blame turns up
commit 76c4b250080fff6e4befaa3619942422fd0ea380
Author: Imre Deak <imre.deak@intel.com>
Date: Tue Apr 1 19:55:22 2014 +0300
drm/i915: move power domain init earlier during system resume
During resume the intel hda audio driver depends on the i915 driver
reinitializing the audio power domain. Since the order of calling the
i915 resume handler wrt. that of the audio driver is not guaranteed,
move the power domain reinitialization step to the resume_early
handler. This is guaranteed to run before the resume handler of any
other driver.
The power domain initialization in turn requires us to enable the i915
pci device first, so move that part earlier too.
Accordingly disabling of the i915 pci device should happen after the
audio suspend handler ran. So move the disabling later from the i915
resume handler to the resume_late handler.
v2:
- move intel_uncore_sanitize/early_sanitize earlier too, so they don't
get reordered wrt. intel_power_domains_init_hw()
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76152
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Takashi Iwai <tiwai@suse.de>
Cc: stable@vger.kernel.org
[danvet: Add cc: stable and loud comments that this is just a hack.]
[danvet: Fix "Should it be static?" sparse warning reported by Wu
Fengguang's kbuilder.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
How does this patch not break stuff?
And a general rule of thumb: If you change anything in the driver load
sequence please digg around in the git historly (with git log --pickaxe
and git blame) to gather evidence for your changes and make sure you don't
break anything.
Thanks, Daniel
> ---
> drivers/gpu/drm/i915/i915_drv.c | 13 +++++++------
> 1 file changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 71be3c9..0e08ec0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -675,6 +675,13 @@ static int i915_drm_resume(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> + intel_uncore_early_sanitize(dev, true);
> +
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> + hsw_disable_pc8(dev_priv);
> +
> + intel_uncore_sanitize(dev);
> +
> if (drm_core_check_feature(dev, DRIVER_MODESET)) {
> mutex_lock(&dev->struct_mutex);
> i915_gem_restore_gtt_mappings(dev);
> @@ -761,12 +768,6 @@ static int i915_drm_resume_early(struct drm_device *dev)
> if (ret)
> DRM_ERROR("Resume prepare failed: %d,Continuing resume\n", ret);
>
> - intel_uncore_early_sanitize(dev, true);
> -
> - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> - hsw_disable_pc8(dev_priv);
> -
> - intel_uncore_sanitize(dev);
> intel_power_domains_init_hw(dev_priv);
>
> return ret;
> --
> 1.8.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v1 2/2] drm/i915: Deferring uncore early sanitize, sanitize, disable pc8 to resume
2014-12-01 9:16 ` Daniel Vetter
@ 2014-12-01 10:29 ` Sagar Arun Kamble
2014-12-01 13:23 ` Imre Deak
0 siblings, 1 reply; 5+ messages in thread
From: Sagar Arun Kamble @ 2014-12-01 10:29 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx, Akash Goel
Thanks Daniel.
This particular commit is moving power_domain_init into resume early.
Does not have details about ordering with uncore early sanitize and
uncore sanitize.
Imre,
Can you please clarify why this ordering with power domain init was
done?
Thanks,
Sagar
On Mon, 2014-12-01 at 10:16 +0100, Daniel Vetter wrote:
> On Mon, Dec 01, 2014 at 12:28:05PM +0530, sagar.a.kamble@intel.com wrote:
> > From: Sagar Kamble <sagar.a.kamble@intel.com>
> >
> > Due to disabling of RC6 in uncore_sanitize in early resume, power is drained
> > till it RC6 is re-enabled post resume.
> > With this change RC6 disabling will be done at beginning of resume only.
> > This helps yield additional power benefits.
> >
> > Signed-off-by: Akash Goel <akash.goel@intel.com>
> > Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
>
> A bit of git blame turns up
>
> commit 76c4b250080fff6e4befaa3619942422fd0ea380
> Author: Imre Deak <imre.deak@intel.com>
> Date: Tue Apr 1 19:55:22 2014 +0300
>
> drm/i915: move power domain init earlier during system resume
>
> During resume the intel hda audio driver depends on the i915 driver
> reinitializing the audio power domain. Since the order of calling the
> i915 resume handler wrt. that of the audio driver is not guaranteed,
> move the power domain reinitialization step to the resume_early
> handler. This is guaranteed to run before the resume handler of any
> other driver.
>
> The power domain initialization in turn requires us to enable the i915
> pci device first, so move that part earlier too.
>
> Accordingly disabling of the i915 pci device should happen after the
> audio suspend handler ran. So move the disabling later from the i915
> resume handler to the resume_late handler.
>
> v2:
> - move intel_uncore_sanitize/early_sanitize earlier too, so they don't
> get reordered wrt. intel_power_domains_init_hw()
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76152
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Reviewed-by: Takashi Iwai <tiwai@suse.de>
> Cc: stable@vger.kernel.org
> [danvet: Add cc: stable and loud comments that this is just a hack.]
> [danvet: Fix "Should it be static?" sparse warning reported by Wu
> Fengguang's kbuilder.]
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>
>
> How does this patch not break stuff?
>
> And a general rule of thumb: If you change anything in the driver load
> sequence please digg around in the git historly (with git log --pickaxe
> and git blame) to gather evidence for your changes and make sure you don't
> break anything.
>
> Thanks, Daniel
>
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 13 +++++++------
> > 1 file changed, 7 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > index 71be3c9..0e08ec0 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -675,6 +675,13 @@ static int i915_drm_resume(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> >
> > + intel_uncore_early_sanitize(dev, true);
> > +
> > + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> > + hsw_disable_pc8(dev_priv);
> > +
> > + intel_uncore_sanitize(dev);
> > +
> > if (drm_core_check_feature(dev, DRIVER_MODESET)) {
> > mutex_lock(&dev->struct_mutex);
> > i915_gem_restore_gtt_mappings(dev);
> > @@ -761,12 +768,6 @@ static int i915_drm_resume_early(struct drm_device *dev)
> > if (ret)
> > DRM_ERROR("Resume prepare failed: %d,Continuing resume\n", ret);
> >
> > - intel_uncore_early_sanitize(dev, true);
> > -
> > - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> > - hsw_disable_pc8(dev_priv);
> > -
> > - intel_uncore_sanitize(dev);
> > intel_power_domains_init_hw(dev_priv);
> >
> > return ret;
> > --
> > 1.8.5
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v1 2/2] drm/i915: Deferring uncore early sanitize, sanitize, disable pc8 to resume
2014-12-01 10:29 ` Sagar Arun Kamble
@ 2014-12-01 13:23 ` Imre Deak
0 siblings, 0 replies; 5+ messages in thread
From: Imre Deak @ 2014-12-01 13:23 UTC (permalink / raw)
To: Sagar Arun Kamble; +Cc: intel-gfx, Akash Goel
On Mon, 2014-12-01 at 15:59 +0530, Sagar Arun Kamble wrote:
> Thanks Daniel.
> This particular commit is moving power_domain_init into resume early.
> Does not have details about ordering with uncore early sanitize and
> uncore sanitize.
>
> Imre,
> Can you please clarify why this ordering with power domain init was
> done?
We call intel_uncore_early_sanitize() and intel_uncore_sanitize() before
any other HW access. They are called from i915_drm_resume_early() since
the hda driver's resume handler can run before i915_drm_resume() is
called. The hda resume handler can in turn request the display power
well resulting in an i915 HW access.
>
> Thanks,
> Sagar
>
> On Mon, 2014-12-01 at 10:16 +0100, Daniel Vetter wrote:
> > On Mon, Dec 01, 2014 at 12:28:05PM +0530, sagar.a.kamble@intel.com wrote:
> > > From: Sagar Kamble <sagar.a.kamble@intel.com>
> > >
> > > Due to disabling of RC6 in uncore_sanitize in early resume, power is drained
> > > till it RC6 is re-enabled post resume.
> > > With this change RC6 disabling will be done at beginning of resume only.
> > > This helps yield additional power benefits.
> > >
> > > Signed-off-by: Akash Goel <akash.goel@intel.com>
> > > Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
> >
> > A bit of git blame turns up
> >
> > commit 76c4b250080fff6e4befaa3619942422fd0ea380
> > Author: Imre Deak <imre.deak@intel.com>
> > Date: Tue Apr 1 19:55:22 2014 +0300
> >
> > drm/i915: move power domain init earlier during system resume
> >
> > During resume the intel hda audio driver depends on the i915 driver
> > reinitializing the audio power domain. Since the order of calling the
> > i915 resume handler wrt. that of the audio driver is not guaranteed,
> > move the power domain reinitialization step to the resume_early
> > handler. This is guaranteed to run before the resume handler of any
> > other driver.
> >
> > The power domain initialization in turn requires us to enable the i915
> > pci device first, so move that part earlier too.
> >
> > Accordingly disabling of the i915 pci device should happen after the
> > audio suspend handler ran. So move the disabling later from the i915
> > resume handler to the resume_late handler.
> >
> > v2:
> > - move intel_uncore_sanitize/early_sanitize earlier too, so they don't
> > get reordered wrt. intel_power_domains_init_hw()
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76152
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > Reviewed-by: Takashi Iwai <tiwai@suse.de>
> > Cc: stable@vger.kernel.org
> > [danvet: Add cc: stable and loud comments that this is just a hack.]
> > [danvet: Fix "Should it be static?" sparse warning reported by Wu
> > Fengguang's kbuilder.]
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> >
> >
> > How does this patch not break stuff?
> >
> > And a general rule of thumb: If you change anything in the driver load
> > sequence please digg around in the git historly (with git log --pickaxe
> > and git blame) to gather evidence for your changes and make sure you don't
> > break anything.
> >
> > Thanks, Daniel
> >
> > > ---
> > > drivers/gpu/drm/i915/i915_drv.c | 13 +++++++------
> > > 1 file changed, 7 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > > index 71be3c9..0e08ec0 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > @@ -675,6 +675,13 @@ static int i915_drm_resume(struct drm_device *dev)
> > > {
> > > struct drm_i915_private *dev_priv = dev->dev_private;
> > >
> > > + intel_uncore_early_sanitize(dev, true);
> > > +
> > > + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> > > + hsw_disable_pc8(dev_priv);
> > > +
> > > + intel_uncore_sanitize(dev);
> > > +
> > > if (drm_core_check_feature(dev, DRIVER_MODESET)) {
> > > mutex_lock(&dev->struct_mutex);
> > > i915_gem_restore_gtt_mappings(dev);
> > > @@ -761,12 +768,6 @@ static int i915_drm_resume_early(struct drm_device *dev)
> > > if (ret)
> > > DRM_ERROR("Resume prepare failed: %d,Continuing resume\n", ret);
> > >
> > > - intel_uncore_early_sanitize(dev, true);
> > > -
> > > - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> > > - hsw_disable_pc8(dev_priv);
> > > -
> > > - intel_uncore_sanitize(dev);
> > > intel_power_domains_init_hw(dev_priv);
> > >
> > > return ret;
> > > --
> > > 1.8.5
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
>
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2014-12-01 13:24 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-12-01 6:58 [PATCH v1 1/2] drm/i915: Enabling RC6 immediately instead of enabling via delayed work item sagar.a.kamble
2014-12-01 6:58 ` [PATCH v1 2/2] drm/i915: Deferring uncore early sanitize, sanitize, disable pc8 to resume sagar.a.kamble
2014-12-01 9:16 ` Daniel Vetter
2014-12-01 10:29 ` Sagar Arun Kamble
2014-12-01 13:23 ` Imre Deak
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