Re: [PATCH 2/2] drm/i915/skl: Implementation of SKL display power well support

[Imre Deak <imre.deak@intel.com>]

On ke, 2015-02-04 at 13:53 +0000, Damien Lespiau wrote:
> On Tue, Feb 03, 2015 at 01:06:31AM +0200, Imre Deak wrote:
> > > +static struct i915_power_well skl_power_wells[] = {
> > > +	{
> > > +		.name = "always-on",
> > > +		.always_on = 1,
> > > +		.domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
> > > +		.ops = &i9xx_always_on_power_well_ops,
> > > +	},
> > > +	{
> > > +		.name = "power well 1",
> > > +		.domains = SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS,
> > > +		.ops = &skl_power_well_ops,
> > > +		.data = SKL_DISP_PW_1,
> > > +	},
> 
> snip
> 
> > > +	{
> > > +		.name = "MISC IO power well",
> > > +		.domains = SKL_DISPLAY_MISC_IO_POWER_DOMAINS,
> > > +		.ops = &skl_power_well_ops,
> > > +		.data = SKL_DISP_PW_MISC_IO,
> > > +	}
> > 
> > Again, since the recent bspec change the misc IO power well should be
> > enabled before anything else, so it needs to be listed before "power
> > well 1" on the list.
> 
> So this one was causing problems. When I try to enabled MISC IO before
> PW1, the request times out. Enabling MISC IO just right after PW1 seems
> to work fine though.

Ok. Bspec doesn't say anything about the ordering between PW1 and MISC
IO, just that you have to enable them together and wait for PG1 fuse
afterwards. How about then moving the MISC IO power well right after PW1
in the list and wait for the PG1 fuse after enabling MISC IO?

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