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From: Yu Zhang <yu.c.zhang@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: daniel.vetter@ffwll.ch
Subject: [PATCH v4 8/8] drm/i915: Support alias ppgtt in VM if ppgtt is enabled
Date: Tue, 10 Feb 2015 19:05:54 +0800	[thread overview]
Message-ID: <1423566354-5532-9-git-send-email-yu.c.zhang@linux.intel.com> (raw)
In-Reply-To: <1423566354-5532-1-git-send-email-yu.c.zhang@linux.intel.com>

The current Intel GVT-g only supports alias ppgtt. And the
emulation is done in the host by first trapping PP_DIR_BASE
mmio accesses. Updating PP_DIR_BASE by using instructions such
as MI_LOAD_REGISTER_IMM are hard to detect and are not supported
in current code. Therefore this patch also adds a new callback
routine - vgpu_mm_switch() to set the PP_DIR_BASE by mmio writes.

v2:
take Chris' comments:
        - move the code into sanitize_enable_ppgtt()
v4:
take Tvrtko's comments:
        - fix the parenthesis alignment warning

Signed-off-by: Yu Zhang <yu.c.zhang@linux.intel.com>
Signed-off-by: Jike Song <jike.song@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 057f905..e54b2a0 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -104,6 +104,9 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
 	has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
 	has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
 
+	if (intel_vgpu_active(dev))
+		has_full_ppgtt = false; /* emulation is too hard */
+
 	/*
 	 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
 	 * execlists, the sole mechanism available to submit work.
@@ -798,6 +801,16 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
 	return 0;
 }
 
+static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
+			  struct intel_engine_cs *ring)
+{
+	struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
+
+	I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
+	I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
+	return 0;
+}
+
 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
 			  struct intel_engine_cs *ring)
 {
@@ -1127,6 +1140,9 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 	} else
 		BUG();
 
+	if (intel_vgpu_active(dev))
+		ppgtt->switch_mm = vgpu_mm_switch;
+
 	ret = gen6_ppgtt_alloc(ppgtt);
 	if (ret)
 		return ret;
-- 
1.9.1

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  parent reply	other threads:[~2015-02-10 11:39 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-02-10 11:05 [PATCH v4 0/8] Add enlightenments for vGPU Yu Zhang
2015-02-10 11:05 ` [PATCH v4 1/8] drm/i915: Introduce a PV INFO page structure for Intel GVT-g Yu Zhang
2015-03-11  6:43   ` Dave Airlie
2015-02-10 11:05 ` [PATCH v4 2/8] drm/i915: Adds graphic address space ballooning logic Yu Zhang
2015-02-10 11:05 ` [PATCH v4 3/8] drm/i915: Partition the fence registers for vGPU in i915 driver Yu Zhang
2015-02-10 11:05 ` [PATCH v4 4/8] drm/i915: Disable framebuffer compression for i915 driver in VM Yu Zhang
2015-02-10 11:05 ` [PATCH v4 5/8] drm/i915: Add the display switch logic for vGPU in i915 driver Yu Zhang
2015-02-10 11:05 ` [PATCH v4 6/8] drm/i915: Disable power management for i915 driver in VM Yu Zhang
2015-02-10 11:05 ` [PATCH v4 7/8] drm/i915: Create vGPU specific MMIO operations to reduce traps Yu Zhang
2015-02-10 11:05 ` Yu Zhang [this message]
2015-02-10 12:11 ` [PATCH v4 0/8] Add enlightenments for vGPU Tvrtko Ursulin
2015-02-11  7:47   ` Yu, Zhang
2015-02-11  8:06   ` Daniel Vetter
2015-02-11  8:12     ` Yu, Zhang

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