From: Thomas Daniel <thomas.daniel@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH] drm/i915: Shift driver's HWSP usage out of reserved range
Date: Wed, 18 Feb 2015 11:48:21 +0000 [thread overview]
Message-ID: <1424260101-18122-1-git-send-email-thomas.daniel@intel.com> (raw)
As of Gen6, the general purpose area of the hardware status page has shrunk and
now begins at dword 0x30. i915 driver uses dword 0x20 to store the seqno which
is now reserved. So shift our HWSP dwords up into the general purpose range
before this bites us.
Signed-off-by: Thomas Daniel <thomas.daniel@intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.h | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index b6c484f..39183fc 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -373,11 +373,12 @@ intel_write_status_page(struct intel_engine_cs *ring,
* 0x06: ring 2 head pointer (915-class)
* 0x10-0x1b: Context status DWords (GM45)
* 0x1f: Last written status offset. (GM45)
+ * 0x20-0x2f: Reserved (Gen6+)
*
- * The area from dword 0x20 to 0x3ff is available for driver usage.
+ * The area from dword 0x30 to 0x3ff is available for driver usage.
*/
-#define I915_GEM_HWS_INDEX 0x20
-#define I915_GEM_HWS_SCRATCH_INDEX 0x30
+#define I915_GEM_HWS_INDEX 0x30
+#define I915_GEM_HWS_SCRATCH_INDEX 0x40
#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
--
1.7.9.5
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next reply other threads:[~2015-02-18 11:48 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-18 11:48 Thomas Daniel [this message]
2015-02-18 14:22 ` [PATCH] drm/i915: Shift driver's HWSP usage out of reserved range shuang.he
2015-02-19 14:58 ` Dave Gordon
2015-02-23 23:27 ` Daniel Vetter
2015-02-24 10:20 ` Daniel, Thomas
2015-02-24 10:51 ` Daniel Vetter
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