From: deepak.s@linux.intel.com
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH v2 4/4] drm/i915: Setup static bias for GPU
Date: Thu, 19 Mar 2015 19:44:29 +0530 [thread overview]
Message-ID: <1426774469-11170-5-git-send-email-deepak.s@linux.intel.com> (raw)
In-Reply-To: <1426774469-11170-1-git-send-email-deepak.s@linux.intel.com>
From: Deepak S <deepak.s@linux.intel.com>
Based on the spec, Setting up static BIAS for GPU to improve the
rps performace.
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++++
drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++++++
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5b84ee6..575d021 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -670,6 +670,11 @@ enum skl_disp_power_wells {
#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
+#define VLV_IOSFB_RPS_OVERRIDE 0x04
+#define VLV_OVERRIDE_RPS_MASK 1
+#define VLV_ENABLE_BIAS_SHARE (1 << 1)
+#define VLV_BIAS_VAL (6 << 2)
+
#define VLV_CZ_CLOCK_TO_MILLI_SEC 100000
#define VLV_RP_UP_EI_THRESHOLD 90
#define VLV_RP_DOWN_EI_THRESHOLD 70
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b9b4d16..7210419 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5016,6 +5016,12 @@ static void cherryview_enable_rps(struct drm_device *dev)
GEN6_RP_UP_BUSY_AVG |
GEN6_RP_DOWN_IDLE_AVG);
+ /* Setting Fixed Bias */
+ val = VLV_OVERRIDE_RPS_MASK |
+ VLV_ENABLE_BIAS_SHARE |
+ VLV_BIAS_VAL;
+ vlv_punit_write(dev_priv, VLV_IOSFB_RPS_OVERRIDE, val);
+
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
/* RPS code assumes GPLL is used */
@@ -5100,6 +5106,12 @@ static void valleyview_enable_rps(struct drm_device *dev)
I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
+ /* Setting Fixed Bias */
+ val = VLV_OVERRIDE_RPS_MASK |
+ VLV_ENABLE_BIAS_SHARE |
+ VLV_BIAS_VAL;
+ vlv_punit_write(dev_priv, VLV_IOSFB_RPS_OVERRIDE, val);
+
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
/* RPS code assumes GPLL is used */
--
1.9.1
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next prev parent reply other threads:[~2015-03-19 14:17 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-19 14:14 [PATCH v2 0/4] CHV PM fix & Improvements deepak.s
2015-03-19 14:14 ` [PATCH v2 1/4] drm/i915/chv: Remove Wait for a previous gfx force-off deepak.s
2015-03-19 14:14 ` [PATCH v2 2/4] drm/i915: Re-adjusting rc6 promotional timer for chv deepak.s
2015-03-26 21:02 ` Paulo Zanoni
2015-03-27 4:56 ` Deepak S
2015-03-19 14:14 ` [PATCH v2 3/4] drm/i915/chv: Set min freq to efficient frequency on chv deepak.s
2015-03-26 21:32 ` Paulo Zanoni
2015-03-26 21:43 ` Chris Wilson
2015-03-27 4:54 ` Deepak S
2015-03-19 14:14 ` deepak.s [this message]
2015-03-20 2:01 ` [PATCH v2 4/4] drm/i915: Setup static bias for GPU shuang.he
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