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From: Anuj Phogat <anuj.phogat@gmail.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 2/5] i965/skl: Move tile_width computations out of drm_intel_gem_bo_tile_pitch
Date: Mon, 30 Mar 2015 14:00:05 -0700	[thread overview]
Message-ID: <1427749208-8961-3-git-send-email-anuj.phogat@gmail.com> (raw)
In-Reply-To: <1427749208-8961-1-git-send-email-anuj.phogat@gmail.com>

This will be utilized by next patch in this series.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
---
 intel/intel_bufmgr_gem.c | 23 ++++++++++-------------
 1 file changed, 10 insertions(+), 13 deletions(-)

diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 5a67f53..af44ba5 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -324,9 +324,9 @@ drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
  */
 static unsigned long
 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
-			    unsigned long pitch, uint32_t *tiling_mode)
+			    unsigned long pitch, unsigned long tile_width,
+			    uint32_t *tiling_mode)
 {
-	unsigned long tile_width;
 	unsigned long i;
 
 	/* If untiled, then just align it so that we can do rendering
@@ -335,13 +335,6 @@ drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
 	if (*tiling_mode == I915_TILING_NONE)
 		return ALIGN(pitch, 64);
 
-	if (*tiling_mode == I915_TILING_X
-			|| (IS_915(bufmgr_gem->pci_device)
-			    && *tiling_mode == I915_TILING_Y))
-		tile_width = 512;
-	else
-		tile_width = 128;
-
 	/* 965 is flexible */
 	if (bufmgr_gem->gen >= 4)
 		return ROUND_UP_TO(pitch, tile_width);
@@ -816,7 +809,7 @@ drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
 			     unsigned long *pitch, unsigned long flags)
 {
 	drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
-	unsigned long size, stride;
+	unsigned long size, stride, tile_width;
 	uint32_t tiling;
 
 	do {
@@ -842,14 +835,18 @@ drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
 			height_alignment = 16;
 		else if (tiling == I915_TILING_X
 			|| (IS_915(bufmgr_gem->pci_device)
-			    && tiling == I915_TILING_Y))
+			    && tiling == I915_TILING_Y)) {
 			height_alignment = 8;
-		else if (tiling == I915_TILING_Y)
+			tile_width = 512;
+		} else if (tiling == I915_TILING_Y)
 			height_alignment = 32;
+			tile_width = 128;
+		}
 		aligned_y = ALIGN(y, height_alignment);
 
 		stride = x * cpp;
-		stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
+		stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride,
+						     tile_width, tiling_mode);
 		size = stride * aligned_y;
 		size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
 	} while (*tiling_mode != tiling);
-- 
2.3.4

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  parent reply	other threads:[~2015-03-30 21:01 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-30 21:00 [PATCH 0/5] i965/skl: Add YF/YS tiling support Anuj Phogat
2015-03-30 21:00 ` [PATCH 1/5] i965/skl: Add macros for Yf/Ys tiling formats Anuj Phogat
2015-03-31 13:17   ` Daniel Vetter
2015-03-31 22:16     ` Anuj Phogat
2015-03-30 21:00 ` Anuj Phogat [this message]
2015-03-30 21:00 ` [PATCH 3/5] i965/skl: Set tile width and height for YF/YS tiling Anuj Phogat
2015-03-31  8:36   ` Tvrtko Ursulin
2015-03-30 21:00 ` [PATCH 4/5] Align YS tile base address to 64KB Anuj Phogat
2015-03-31 14:26   ` Damien Lespiau
2015-03-31 17:49     ` Anuj Phogat
2015-03-31 17:57       ` Damien Lespiau
2015-04-01  6:11         ` Daniel Vetter
2015-04-01 16:31           ` Anuj Phogat
2015-03-30 21:00 ` [PATCH 5/5] build: Bump the version to 2.4.61 Anuj Phogat
2015-03-31 14:28   ` Damien Lespiau
2015-03-31 17:51     ` Anuj Phogat
2015-04-01  6:13       ` Daniel Vetter

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